公开(公告)号：US20180342394A1

公开(公告)日：2018-11-29

申请号：US15603465

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi Qiang Mu ,  Chow Yee Lim ,  Hui Yang ,  YONG BIN FAN ,  JIANJUN YANG ,  Chih-Chien Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.

公开(公告)号：US10141194B1

公开(公告)日：2018-11-27

申请号：US15603465

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi Qiang Mu ,  Chow Yee Lim ,  Hui Yang ,  Yong Bin Fan ,  Jianjun Yang ,  Chih-Chien Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28273 ,  H01L21/02071 ,  H01L21/02074 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.