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1.发明授权公开(公告)号：US11270439B2
公开(公告)日：2022-03-08
申请号：US17250947
申请日：2019-10-09
摘要： A histogram-based method for auto segmentation of integrated circuit structures is disclosed. The method includes an auto-segmentation process/algorithm, which works on the histogram of the SEM image and does not try to model the noise sources or the features. The auto-segmentation process/algorithm extracts the number of peaks in the histogram from low magnification SEM images or SEM images not necessarily having high quality images, significantly simplifies the traditionally lengthy and expensive IC reverse engineering efforts. Hence, the size of the image does not affect the final segmentation. The auto-segmentation process/algorithm performs the steps of: extract a first histogram from the first SEM image; identifying boundaries of the plurality of structural elements in the IC based at least in part on an output of the first histogram; and auto-segmenting the first SEM image into the plurality of structural elements.
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公开(公告)号：US20220028086A1
公开(公告)日：2022-01-27
申请号：US17378438
申请日：2021-07-16
摘要： Various embodiments of the present disclosure provide for accelerated segmentation for reverse engineering of integrated circuits. In one example, an embodiment provides for receiving an SEM image for an integrated circuit, performing filtering and binarization with respect to the SEM image, extracting information associated with filter sizes for the filtering, extracting signatures related to a distribution for background pixels and foreground pixels of the SEM image, extracting respective distance to mean signatures for the background pixels and the foreground pixels, and segmenting the SEM image based at least in part on the filter sizes and the respective distance to mean signatures to generate a segmented image for the integrated circuit.
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公开(公告)号：US11893742B2
公开(公告)日：2024-02-06
申请号：US17378438
申请日：2021-07-16
CPC分类号： G06T7/11 , G06T5/20 , G06T7/136 , G06T7/194 , G06T7/40 , G06T2207/10061 , G06T2207/20212 , G06T2207/30148
摘要： Various embodiments of the present disclosure provide for accelerated segmentation for reverse engineering of integrated circuits. In one example, an embodiment provides for receiving an SEM image for an integrated circuit, performing filtering and binarization with respect to the SEM image, extracting information associated with filter sizes for the filtering, extracting signatures related to a distribution for background pixels and foreground pixels of the SEM image, extracting respective distance to mean signatures for the background pixels and the foreground pixels, and segmenting the SEM image based at least in part on the filter sizes and the respective distance to mean signatures to generate a segmented image for the integrated circuit.
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公开(公告)号：US11030348B2
公开(公告)日：2021-06-08
申请号：US16309239
申请日：2017-06-15
IPC分类号： G06F21/75 , G06F21/76 , H01L21/762 , H01L23/00 , G06F30/39 , G06F30/327 , G06F30/394 , G06F30/333
摘要： Circuits and methods for protecting against intellectual property piracy and integrated circuit piracy from an untrusted third party are provided. A circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing the output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit. In addition, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.
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公开(公告)号：US20210081574A1
公开(公告)日：2021-03-18
申请号：US17008722
申请日：2020-09-01
摘要： Embodiments of the present disclosure provide methods, systems, apparatus, and computer program products are for detecting whether a suspect component such as an integrated circuit (IC) or a system-on-chip (SoC) is recycled. Specifically, various embodiments involve processing power supply rejection ratio (PSRR) data obtained from a low drop-out regulator (LDO) used for the suspect component using a recycle detection machine learning model to generate a recycle prediction. In particular embodiments, the recycle detection machine learning model is developed based at least in part on degradation of PSRRs of LDOs. Accordingly, a determination is made as to whether the suspect component is recycled based on the recycle prediction. If so, then an indication that the suspect component is recycled is provided.
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公开(公告)号：US20190311156A1
公开(公告)日：2019-10-10
申请号：US16309239
申请日：2017-06-15
摘要： Circuits and methods for protecting against intellectual property piracy and integrated circuit piracy from an untrusted third party are provided. A circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing the output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit. In addition, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.
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公开(公告)号：US20180166399A1
公开(公告)日：2018-06-14
申请号：US15838647
申请日：2017-12-12
CPC分类号： H01L23/57 , G01R31/2851 , G06F21/60 , G06F21/70 , G06F21/87 , H01L23/00 , H01L23/576
摘要： A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets. The milling exclusion area is an area that microprobing attack does not succeed without cutting off at least one of the rectangular segments
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公开(公告)号：US11776093B2
公开(公告)日：2023-10-03
申请号：US16923255
申请日：2020-07-08
摘要： Systems and methods are configured to generate a frequency map representing a density of objects found in regions of a sample that may be used in setting parameters for imaging the regions. Various embodiments involve binarizing the pixels for a raw image of the sample to transform the image into binary data. Run-length encoded components are identified from the data for dimensions of the raw image. Each component is a length of a sequence of adjacent pixels found in a dimension with the same value in the binary data. A projection of the image is then generated from projection values for the dimensions. Each projection value provides a measure of the density of objects present in a dimension with respect to the components identified for the dimension. This projection is used to identify a level of density for each region of the sample from which the frequency map is generated.
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公开(公告)号：US20200251602A1
公开(公告)日：2020-08-06
申请号：US16775178
申请日：2020-01-28
IPC分类号： H01L31/0236 , H01L23/00 , H01L23/532 , H01L21/768 , G01R31/311
摘要： A pyramid structure to mitigate optical probing attacks in ICs by scrambling the measurements reflected by a laser pulse is disclosed. The pyramid structure is applied to selected areas at the bottom surface of the metal traces in metal layer to circumvent the extra silicon layer and thus minimize the changes to the conventional device structures. The pyramid structure includes randomized pyramids at nanometer scale. Optical simulation results show the pyramidized metal surface is able to prevent optical probing attacks. The fabrication of pyramids is CMOS compatible as well. Optical simulations are performed to analyze the impact these nano-scaled pyramids in a laser voltage probing attacking model. The nanopyramid can disturb the optical measurements enough to make the attacks practically infeasible. In addition, the nanopyramid structure countermeasure works in a passive mode without consuming any energy.
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公开(公告)号：US10573605B2
公开(公告)日：2020-02-25
申请号：US15838647
申请日：2017-12-12
摘要： A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets. The milling exclusion area is an area that microprobing attack does not succeed without cutting off at least one of the rectangular segments.
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