公开(公告)号：US20190051585A1

公开(公告)日：2019-02-14

申请号：US16057792

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan DIMAANO JR. ,  Nataporn CHARUSABHA ,  Saravuth SIRINORAKUL ,  Preecha JOYMAK ,  Roel Adeva ROBLES

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

Abstract: Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.

公开(公告)号：US20200321273A1

公开(公告)日：2020-10-08

申请号：US16886728

申请日：2020-05-28

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong TAN ,  Wilson Poh Leng ONG ,  Kriangsak Sae LE ,  Saravuth SIRINORAKUL ,  Somsak PHUKRONGHIN ,  Paweena PHATTO

IPC: H01L23/498 ,  H01L23/16 ,  H01L23/31 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L23/055 ,  H01L23/04 ,  H01L23/24

Abstract: A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

公开(公告)号：US20220028798A1

公开(公告)日：2022-01-27

申请号：US17382283

申请日：2021-07-21

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth SIRINORAKUL ,  Il Kwon SHIM ,  Kok Chuen LOCK ,  Roel Adeva ROBLES ,  Eakkasit DUMSONG

IPC: H01L23/552 ,  H01L23/36 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56

Abstract: The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.

公开(公告)号：US20210035891A1

公开(公告)日：2021-02-04

申请号：US16942715

申请日：2020-07-29

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Wing Keung LAM ,  Saravuth SIRINORAKUL ,  Kok Chuen LOCK ,  Roel Adeva ROBLES

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L25/16

Abstract: An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.

公开(公告)号：US20190043797A1

公开(公告)日：2019-02-07

申请号：US16056541

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong TAN ,  Wilson Poh Leng ONG ,  Kriangsak Sae LE ,  Saravuth SIRINORAKUL ,  Somsak PHUKRONGHIN ,  Paweena PHATTO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/055 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56

Abstract: An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.