公开(公告)号：US20220328685A1

公开(公告)日：2022-10-13

申请号：US17852371

申请日：2022-06-29

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

公开(公告)号：US11735657B2

公开(公告)日：2023-08-22

申请号：US17852371

申请日：2022-06-29

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7825 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/6656

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

公开(公告)号：US20170025422A1

公开(公告)日：2017-01-26

申请号：US14807882

申请日：2015-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Sung-Bin Lin ,  Cherng-En Sun

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L29/0653 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

Abstract translation: 捕获门形成工艺包括以下。 在基板上形成氧化物/氮化物/氧化物层。 形成硬掩模以覆盖氧化物/氮化物/氧化物层。 图案化硬掩模，氧化物/氮化物/氧化物层和衬底以在硬掩模中形成至少沟槽，沿第一方向形成氧化物/氮化物/氧化物层。 在沟槽中形成隔离结构。 沿着与第一方向正交的第二方向跨越氧化物/氮化物/氧化物层形成第一栅极。 由所述工艺形成的闪光单元包括衬底，第一栅极和氧化物/氮化物/氧化物层。 基板至少包括沿第一方向延伸的有效区域。 第一栅极沿着与第一方向正交的第二方向跨越有源区域布置，从而与重叠区域相交。 氧化物/氮化物/氧化物层设置在第一栅极和有源区域之间的重叠区域中。

公开(公告)号：US11417761B1

公开(公告)日：2022-08-16

申请号：US17171760

申请日：2021-02-09

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

公开(公告)号：US20220254924A1

公开(公告)日：2022-08-11

申请号：US17171760

申请日：2021-02-09

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substrate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

公开(公告)号：US10096611B2

公开(公告)日：2018-10-09

申请号：US14807882

申请日：2015-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Sung-Bin Lin ,  Cherng-En Sun

IPC: H01L27/115 ,  H01L29/792 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/06

Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.