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    NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    非易失性存储器结构及其制造方法

    公开(公告)号：US20140175531A1

    公开(公告)日：2014-06-26

    申请号：US13723159

    申请日：2012-12-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Huang ,  Shen-De Wang ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Chien-Hung Chen

    IPC: H01L29/66 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/792

    Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

    Abstract translation: 一种用于制造非易失性存储结构的方法包括提供具有栅极结构的衬底，执行第一氧化工艺以形成至少覆盖导电层的底角的第一SiO层，执行第一蚀刻工艺以除去第一 SiO层和所述电介质层的一部分以形成空腔，执行第二氧化工艺以形成覆盖所述空腔的侧壁的第二SiO层和覆盖所述衬底的表面的第三SiO层，形成填充在所述腔中的第一SiN层 并且覆盖衬底上的栅极结构，并且去除第一SiN层的一部分以形成SiN结构，其包括填充在空腔中的脚部和从脚部向上延伸的勃起部，以及覆盖侧壁的安装部 门结构。

    Non-volatile memory device with undercut ONO trapping structure and manufacturing method thereof
    3.
    发明授权
    Non-volatile memory device with undercut ONO trapping structure and manufacturing method thereof 有权
    具有底切ONO捕获结构的非易失性存储器件及其制造方法

    公开(公告)号：US09331185B2

    公开(公告)日：2016-05-03

    申请号：US14505513

    申请日：2014-10-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Huang ,  Shen-De Wang ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Chien-Hung Chen

    IPC: H01L21/336 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

    CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/792

    Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

    Abstract translation: 一种用于制造非易失性存储结构的方法包括提供具有栅极结构的衬底，执行第一氧化工艺以形成至少覆盖导电层的底角的第一SiO层，执行第一蚀刻工艺以除去第一 SiO层和所述电介质层的一部分以形成空腔，执行第二氧化工艺以形成覆盖所述空腔的侧壁的第二SiO层和覆盖所述衬底的表面的第三SiO层，形成填充在所述腔中的第一SiN层 并且覆盖衬底上的栅极结构，并且去除第一SiN层的一部分以形成SiN结构，其包括填充在空腔中的脚部和从脚部向上延伸的勃起部，以及覆盖侧壁的安装部 门结构。

    NONVOLATILE MEMORY AND MANIPULATING METHOD THEREOF
    4.
    发明申请
    NONVOLATILE MEMORY AND MANIPULATING METHOD THEREOF 有权
    非易失性存储器及其操作方法

    公开(公告)号：US20140198574A1

    公开(公告)日：2014-07-17

    申请号：US13741442

    申请日：2013-01-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

    IPC: G11C16/14 ,  G11C16/10 ,  H01L27/088

    CPC classification number: G11C16/14 ,  G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/088 ,  H01L27/11565 ,  H01L27/11568

    Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

    Abstract translation: 提供了一种非易失性存储器的操作方法，包括以下步骤。 提供具有多个存储单元的非易失性存储器。 两个相邻的存储器单元对应于一个位，并且包括基板，第一和第二第一掺杂区域，第二掺杂区域，电荷俘获层，控制栅极，第一位线，源极线和与 第一个位线。 形成第一和第二通道。 电荷捕获层设置在第一和第二通道上。 通过以下步骤对相邻的两个存储单元进行编程。 第一正电压和负电压分别施加到第一和第二掺杂区域之间的控制栅极以及第二和第二掺杂区域之间的控制栅极。 第一个电压被施加到源极线。

    Method for fabricating transistor structure
    6.
    发明授权
    Method for fabricating transistor structure 有权

    公开(公告)号：US11735657B2

    公开(公告)日：2023-08-22

    申请号：US17852371

    申请日：2022-06-29

    Applicant: United Microelectronics Corp.

    Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

    IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

    CPC classification number: H01L29/7825 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/6656

    Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

    Semiconductor device and method for fabricating the same
    7.
    发明授权
    Semiconductor device and method for fabricating the same 有权

    公开(公告)号：US10515976B2

    公开(公告)日：2019-12-24

    申请号：US15885878

    申请日：2018-02-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Chung Chang ,  Tzu-Ping Chen

    IPC: H01L27/11575 ,  H01L27/11573 ,  H01L27/11568 ,  H01L29/51 ,  H01L21/28

    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

    TRAPPING GATE FORMING PROCESS AND FLASH CELL
    8.
    发明申请
    TRAPPING GATE FORMING PROCESS AND FLASH CELL 审中-公开
    捕获栅格形成过程和闪存

    公开(公告)号：US20170025422A1

    公开(公告)日：2017-01-26

    申请号：US14807882

    申请日：2015-07-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Chung Chang ,  Sung-Bin Lin ,  Cherng-En Sun

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/06 ,  H01L29/423

    CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L29/0653 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

    Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

    Abstract translation: 捕获门形成工艺包括以下。 在基板上形成氧化物/氮化物/氧化物层。 形成硬掩模以覆盖氧化物/氮化物/氧化物层。 图案化硬掩模，氧化物/氮化物/氧化物层和衬底以在硬掩模中形成至少沟槽，沿第一方向形成氧化物/氮化物/氧化物层。 在沟槽中形成隔离结构。 沿着与第一方向正交的第二方向跨越氧化物/氮化物/氧化物层形成第一栅极。 由所述工艺形成的闪光单元包括衬底，第一栅极和氧化物/氮化物/氧化物层。 基板至少包括沿第一方向延伸的有效区域。 第一栅极沿着与第一方向正交的第二方向跨越有源区域布置，从而与重叠区域相交。 氧化物/氮化物/氧化物层设置在第一栅极和有源区域之间的重叠区域中。

    Memory cell structure and method for forming the same
    9.
    发明授权
    Memory cell structure and method for forming the same 有权
    记忆单元结构及其形成方法

    公开(公告)号：US09136276B1

    公开(公告)日：2015-09-15

    申请号：US14255977

    申请日：2014-04-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Huang ,  Sung-Bin Lin ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Yen-Ting Ho ,  Chien-Hung Chen

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L27/11573 ,  H01L29/42348 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

    Abstract: A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.

    Abstract translation: 一种用于形成存储单元结构的方法包括以下步骤。 提供至少包括限定在其上的存储单元区域的衬底，并且在存储单元区域中形成第一栅极堆叠。 执行第一LDD注入以在存储单元区域中的第一栅极堆叠的一侧形成第一LDD，并且第一LDD包括第一导电类型。 执行第二LDD注入以在存储单元区域中与第一LDD相对的第一栅极堆叠的一侧处形成第二LDD，并且第二LDD包括第一导电类型。 第一LDD和第二LDD彼此不同。

    Transistor structure and method for fabricating the same
    10.
    发明授权
    Transistor structure and method for fabricating the same 有权

    公开(公告)号：US11417761B1

    公开(公告)日：2022-08-16

    申请号：US17171760

    申请日：2021-02-09

    Applicant: United Microelectronics Corp.

    Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

    Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

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