公开(公告)号：US10096611B2

公开(公告)日：2018-10-09

申请号：US14807882

申请日：2015-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Sung-Bin Lin ,  Cherng-En Sun

IPC: H01L27/115 ,  H01L29/792 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/06

Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

公开(公告)号：US10510758B2

公开(公告)日：2019-12-17

申请号：US15725275

申请日：2017-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: H01L21/30 ,  H01L27/105 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11517 ,  H01L29/51 ,  H01L29/423 ,  H01L29/788

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.

公开(公告)号：US09530511B1

公开(公告)日：2016-12-27

申请号：US14969584

申请日：2015-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/04 ,  H01L29/792 ,  H01L29/423 ,  G11C16/10 ,  H01L29/51

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/10 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/518 ,  H01L29/792

Abstract: An operating method of a memory device includes providing the memory device and performing an erase operation. The memory device includes a substrate, a gate dielectric layer formed on the substrate, a gate conductive layer formed on the gate dielectric layer, a charge trapping layer, a charge blocking layer, a source region, and a drain region. The charge trapping layer has a vertical portion formed on a sidewall of the gate conductive layer and a horizontal portion formed between the substrate and the gate conductive layer. The charge blocking layer is formed between the substrate and the charge trapping layer. The source and drain regions are formed in the substrate and located at two sides of the gate conductive layer respectively. Performing the erase operation includes applying an erase voltage to the gate conductive layer for inducing a BBHH injection and a FN hole tunneling.

Abstract translation: 存储器件的操作方法包括提供存储器件并执行擦除操作。 存储器件包括衬底，形成在衬底上的栅极电介质层，形成在栅极介电层上的栅极导电层，电荷俘获层，电荷阻挡层，源极区和漏极区。 电荷捕获层具有形成在栅极导电层的侧壁上的垂直部分和形成在基板和栅极导电层之间的水平部分。 电荷阻挡层形成在基板和电荷俘获层之间。 源极和漏极区分别形成在衬底中并分别位于栅极导电层的两侧。 执行擦除操作包括向栅极导电层施加擦除电压以引起BBHH注入和FN空穴隧穿。

公开(公告)号：US20190103405A1

公开(公告)日：2019-04-04

申请号：US15725275

申请日：2017-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: H01L27/105 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11517

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.

公开(公告)号：US20170317092A1

公开(公告)日：2017-11-02

申请号：US15140029

申请日：2016-04-27

Applicant: United Microelectronics Corp.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: H01L27/11521 ,  H01L29/66 ,  H01L27/11558 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/7835

Abstract: A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

公开(公告)号：US08921888B2

公开(公告)日：2014-12-30

申请号：US14231659

申请日：2014-03-31

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Sung-Bin Lin

IPC: H01L29/739 ,  H01L21/266 ,  H01L29/66 ,  H01L29/73 ,  H01L29/872 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L21/266 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/66272 ,  H01L29/7304 ,  H01L29/872

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，提供半导体衬底，并且在其上限定第一区域，第二区域和第三区域。 然后，分别在第一区域和第二区域的半导体衬底中形成具有第一导电类型的第一阱。 形成与第二区域的第一阱部分重叠的半导体层。 此外，具有第二导电类型的第二阱分别形成在第三区域的半导体衬底和第二区域的第一阱中，其中第二区域的第二阱设置在半导体层下方。

公开(公告)号：US09793278B1

公开(公告)日：2017-10-17

申请号：US15140029

申请日：2016-04-27

Applicant: United Microelectronics Corp.

Inventor： Yen-Ting Ho ,  Sung-Bin Lin

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/7835

Abstract: A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

公开(公告)号：US09659782B2

公开(公告)日：2017-05-23

申请号：US14616747

申请日：2015-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sung-Bin Lin

IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating memory device is disclosed. The method includes the steps of: providing a substrate having a tunnel oxide layer on the substrate, a first electrode layer on the tunnel oxide layer, an oxide-nitride-oxide (ONO) stack on the first electrode layer, and a second electrode layer on the ONO stack, and then removing part of the second electrode layer, part of the ONO stack, and part of the first electrode layer so that the tunnel oxide layer is not exposed.

公开(公告)号：US20170025422A1

公开(公告)日：2017-01-26

申请号：US14807882

申请日：2015-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Sung-Bin Lin ,  Cherng-En Sun

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L29/0653 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

Abstract translation: 捕获门形成工艺包括以下。 在基板上形成氧化物/氮化物/氧化物层。 形成硬掩模以覆盖氧化物/氮化物/氧化物层。 图案化硬掩模，氧化物/氮化物/氧化物层和衬底以在硬掩模中形成至少沟槽，沿第一方向形成氧化物/氮化物/氧化物层。 在沟槽中形成隔离结构。 沿着与第一方向正交的第二方向跨越氧化物/氮化物/氧化物层形成第一栅极。 由所述工艺形成的闪光单元包括衬底，第一栅极和氧化物/氮化物/氧化物层。 基板至少包括沿第一方向延伸的有效区域。 第一栅极沿着与第一方向正交的第二方向跨越有源区域布置，从而与重叠区域相交。 氧化物/氮化物/氧化物层设置在第一栅极和有源区域之间的重叠区域中。

公开(公告)号：US20160197156A1

公开(公告)日：2016-07-07

申请号：US14616747

申请日：2015-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sung-Bin Lin

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/792

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating memory device is disclosed. The method includes the steps of: providing a substrate having a tunnel oxide layer on the substrate, a first electrode layer on the tunnel oxide layer, an oxide-nitride-oxide (ONO) stack on the first electrode layer, and a second electrode layer on the ONO stack, and then removing part of the second electrode layer, part of the ONO stack, and part of the first electrode layer so that the tunnel oxide layer is not exposed.

Abstract translation: 公开了一种用于制造存储器件的方法。 该方法包括以下步骤：提供在衬底上具有隧道氧化物层的衬底，隧道氧化物层上的第一电极层，第一电极层上的氧化物 - 氧化物 - 氧化物（ONO）堆叠以及第二电极层 在ONO堆叠上，然后去除第二电极层的一部分，ONO堆叠的一部分和第一电极层的一部分，使得隧道氧化物层不暴露。