公开(公告)号：US20220328685A1

公开(公告)日：2022-10-13

申请号：US17852371

申请日：2022-06-29

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

公开(公告)号：US09431239B1

公开(公告)日：2016-08-30

申请号：US14809278

申请日：2015-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Nien-Chung Li ,  Ching-Nan Hwang ,  Shih-Teng Huang ,  Ming-Yen Liu

IPC: H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/167 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/823462 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a doped region in the substrate; forming a thermal oxide layer on the substrate and the doped region; removing the thermal oxide layer to form a first recess; forming an epitaxial layer on the substrate and in the first recess; and forming a gate dielectric layer in the epitaxial layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底中形成掺杂区域; 在衬底和掺杂区上形成热氧化层; 去除热氧化物层以形成第一凹槽; 在所述基板和所述第一凹部中形成外延层; 以及在所述外延层中形成栅极电介质层。

公开(公告)号：US11735657B2

公开(公告)日：2023-08-22

申请号：US17852371

申请日：2022-06-29

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7825 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/6656

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

公开(公告)号：US11417761B1

公开(公告)日：2022-08-16

申请号：US17171760

申请日：2021-02-09

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

公开(公告)号：US20220254924A1

公开(公告)日：2022-08-11

申请号：US17171760

申请日：2021-02-09

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substrate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.