公开(公告)号：US20180233510A1

公开(公告)日：2018-08-16

申请号：US15951070

申请日：2018-04-11

Applicant: United Microelectronics Corp.

Inventor： Hui Yang ,  Chow-Yee Lim

IPC: H01L27/11534 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11521 ,  H01L29/45 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11534 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

公开(公告)号：US09972633B2

公开(公告)日：2018-05-15

申请号：US15008185

申请日：2016-01-27

Applicant: United Microelectronics Corp.

Inventor： Hui Yang ,  Chow-Yee Lim

IPC: H01L29/788 ,  H01L27/11534 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/51 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L27/11534 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

公开(公告)号：US20170213839A1

公开(公告)日：2017-07-27

申请号：US15008185

申请日：2016-01-27

Applicant: United Microelectronics Corp.

Inventor： Hui Yang ,  Chow-Yee Lim

IPC: H01L27/115 ,  H01L29/45 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11534 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

公开(公告)号：US10217756B2

公开(公告)日：2019-02-26

申请号：US15951070

申请日：2018-04-11

Applicant: United Microelectronics Corp.

Inventor： Hui Yang ,  Chow-Yee Lim

IPC: H01L29/788 ,  H01L27/11534 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11521 ,  H01L29/45 ,  H01L29/51 ,  H01L21/02

Abstract: A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

公开(公告)号：US09966465B1

公开(公告)日：2018-05-08

申请号：US15631529

申请日：2017-06-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock-Chun Chin ,  Lan-Xiang Wang ,  Hong Liao ,  Chao Jiang ,  Chow-Yee Lim

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L29/78391 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/516 ,  H01L29/7883 ,  H01L29/792

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first dielectric layer, a charge trapping layer, a ferroelectric material layer, and a gate layer. The first dielectric layer is disposed on the substrate, the charge trapping layer is disposed on the first dielectric layer, the ferroelectric material layer is disposed on the charge trapping layer, and the gate layer is disposed on the ferroelectric material layer.