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公开(公告)号：US20180233510A1
公开(公告)日：2018-08-16
申请号：US15951070
申请日：2018-04-11
发明人： Hui Yang , Chow-Yee Lim
IPC分类号： H01L27/11534 , H01L27/11568 , H01L27/11573 , H01L27/11521 , H01L29/45 , H01L21/02 , H01L29/51
CPC分类号： H01L27/11534 , H01L21/02164 , H01L21/0217 , H01L27/11521 , H01L27/11529 , H01L27/11541 , H01L27/11543 , H01L27/11568 , H01L27/11573 , H01L29/45 , H01L29/513 , H01L29/518
摘要： A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
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公开(公告)号：US09972633B2
公开(公告)日：2018-05-15
申请号：US15008185
申请日：2016-01-27
发明人： Hui Yang , Chow-Yee Lim
IPC分类号： H01L29/788 , H01L27/11534 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/51 , H01L29/45 , H01L21/02
CPC分类号： H01L27/11534 , H01L21/02164 , H01L21/0217 , H01L27/11521 , H01L27/11529 , H01L27/11541 , H01L27/11543 , H01L27/11568 , H01L27/11573 , H01L29/45 , H01L29/513 , H01L29/518
摘要： A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
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公开(公告)号：US20170213839A1
公开(公告)日：2017-07-27
申请号：US15008185
申请日：2016-01-27
发明人： Hui Yang , Chow-Yee Lim
IPC分类号： H01L27/115 , H01L29/45 , H01L21/02 , H01L29/51
CPC分类号： H01L27/11534 , H01L21/02164 , H01L21/0217 , H01L27/11521 , H01L27/11529 , H01L27/11541 , H01L27/11543 , H01L27/11568 , H01L27/11573 , H01L29/45 , H01L29/513 , H01L29/518
摘要： A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
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公开(公告)号：US10217756B2
公开(公告)日：2019-02-26
申请号：US15951070
申请日：2018-04-11
发明人： Hui Yang , Chow-Yee Lim
IPC分类号： H01L29/788 , H01L27/11534 , H01L27/11568 , H01L27/11573 , H01L27/11521 , H01L29/45 , H01L29/51 , H01L21/02
摘要： A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
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公开(公告)号：US09607123B2
公开(公告)日：2017-03-28
申请号：US14598236
申请日：2015-01-16
发明人： Xing Hua Zhang , Chi-Fa Ku , Hong Liao , Ye Chao Li , Hui Yang
IPC分类号： G06F17/50 , H01L23/58 , H01L21/66 , H01L23/528 , H01L21/8238 , H01L27/02 , H01L23/10 , H01L27/06 , H01L23/00
CPC分类号： G06F17/5081 , H01L21/823871 , H01L22/34 , H01L23/10 , H01L23/528 , H01L23/562 , H01L23/58 , H01L27/0266 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.
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6.发明申请MONITORING SEMICONDUCTOR DEVICE, METHOD FOR PERFORMING DEEP N-TYPED WELL-CORRELATED (DNW-CORRELATED) ANTENNA RULE CHECK OF INTEGRATED CIRCUIT AND SEMICONDUCTOR STRUCTURE COMPLYING WITH DNW-CORRELATED ANTENNA RULE 有权监测半导体器件，用于执行与DNW相关的天线规则相匹配的集成电路和半导体结构的深度N型相关（DNW相关）天线规则检查的方法公开(公告)号：US20160211187A1
公开(公告)日：2016-07-21
申请号：US14598236
申请日：2015-01-16
发明人： Xing Hua Zhang , Chi-Fa Ku , Hong Liao , Ye Chao Li , Hui Yang
IPC分类号： H01L21/66 , H01L23/10 , H01L23/528 , G06F17/50
CPC分类号： G06F17/5081 , H01L21/823871 , H01L22/34 , H01L23/10 , H01L23/528 , H01L23/562 , H01L23/58 , H01L27/0266 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.
摘要翻译： 半导体监视装置包括基板，形成在基板上的模具密封环，形成在模具密封环下方的基板中的深n型阱，以及与模密封环电连接的监视装置。 监测装置形成在限定在基板上的划线区域中。 深n型井的宽度大于模具密封环的宽度。
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公开(公告)号：US20180342394A1
公开(公告)日：2018-11-29
申请号：US15603465
申请日：2017-05-24
发明人： Zhi Qiang Mu , Chow Yee Lim , Hui Yang , YONG BIN FAN , JIANJUN YANG , Chih-Chien Chang
摘要： A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.
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公开(公告)号：US10141194B1
公开(公告)日：2018-11-27
申请号：US15603465
申请日：2017-05-24
发明人： Zhi Qiang Mu , Chow Yee Lim , Hui Yang , Yong Bin Fan , Jianjun Yang , Chih-Chien Chang
CPC分类号： H01L21/28273 , H01L21/02071 , H01L21/02074 , H01L29/4916 , H01L29/513 , H01L29/518
摘要： A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.
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