公开(公告)号：US09412653B2

公开(公告)日：2016-08-09

申请号：US14817227

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

公开(公告)号：US10153231B2

公开(公告)日：2018-12-11

申请号：US15466847

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US10446489B2

公开(公告)日：2019-10-15

申请号：US16170059

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US20190067184A1

公开(公告)日：2019-02-28

申请号：US16170059

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76871 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US10079177B1

公开(公告)日：2018-09-18

申请号：US15694354

申请日：2017-09-01

Applicant: United Microelectronics Corp.

Inventor： Ko-Wei Lin ,  Ying-Lien Chen ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Hung-Miao Lin ,  Sheng-Yi Su ,  Tzu-Hao Liu

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L21/76873 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76862 ,  H01L23/53238

Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.

公开(公告)号：US20180261537A1

公开(公告)日：2018-09-13

申请号：US15466847

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/76871 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US20150340280A1

公开(公告)日：2015-11-26

申请号：US14817227

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC: H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。