公开(公告)号：US20240105720A1

公开(公告)日：2024-03-28

申请号：US18525909

申请日：2023-12-01

申请人： United Microelectronics Corp.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC分类号： H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66818 ,  H01L21/845

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

公开(公告)号：US20230143927A1

公开(公告)日：2023-05-11

申请号：US18093330

申请日：2023-01-05

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC分类号： H01L29/66 ,  H01L21/762

CPC分类号： H01L29/66628 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/66787

摘要： A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

公开(公告)号：US11527638B2

公开(公告)日：2022-12-13

申请号：US17161696

申请日：2021-01-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/762

摘要： A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.

公开(公告)号：US20210167189A1

公开(公告)日：2021-06-03

申请号：US17161707

申请日：2021-01-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC分类号： H01L29/66 ,  H01L21/762

摘要： A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

公开(公告)号：US10566327B2

公开(公告)日：2020-02-18

申请号：US15691703

申请日：2017-08-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/02 ,  H01L21/762 ,  H01L29/06 ,  H01L21/84

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

公开(公告)号：US10522660B2

公开(公告)日：2019-12-31

申请号：US15690260

申请日：2017-08-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/02

摘要： A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; removing the second gate structure and part of the fin-shaped structure to forma first trench; forming a dielectric layer into the first trench; and planarizing part of the dielectric layer to form a single diffusion break (SDB) structure. Preferably, the top surfaces of the SDB structure and the first gate structure are coplanar.

公开(公告)号：US10347761B2

公开(公告)日：2019-07-09

申请号：US15821860

申请日：2017-11-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Chun-Jung Tang ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L29/167

摘要： A tunnel field effect transistor (TFET) includes: a first gate structure on a substrate; a source region having a first conductive type on one side of the first gate structure; a drain region having a second conductive type on another side of the first gate structure; a first isolation structure adjacent to the source region; and a second isolation structure adjacent to the drain region. Preferably, the first isolation and the second isolation comprise different material and different depths or same material and different depths.

公开(公告)号：US20190157443A1

公开(公告)日：2019-05-23

申请号：US15849599

申请日：2017-12-20

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/027

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first buffer layer on the first fin-shaped structure and the second fin-shaped structure; removing the first buffer layer on the first region; and performing a curing process so that a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.

公开(公告)号：US20180138178A1

公开(公告)日：2018-05-17

申请号：US15375177

申请日：2016-12-12

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Shou-Wei Hsieh ,  Hsin-Yu Chen

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/311

CPC分类号： H01L27/092 ,  H01L21/31144 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/517

摘要： A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

公开(公告)号：US09412653B2

公开(公告)日：2016-08-09

申请号：US14817227

申请日：2015-08-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC分类号： H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

摘要翻译： 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。