公开(公告)号：US10262987B2

公开(公告)日：2019-04-16

申请号：US15481444

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02 ,  H02H9/04

Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

公开(公告)号：US20180358294A1

公开(公告)日：2018-12-13

申请号：US15667637

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5223

Abstract: An electric connector includes a metal interconnect, a first vertical element and a second vertical element. The metal interconnect includes a plurality of horizontal elements. The first vertical element physically connects to a top surface of each of the horizontal elements. The second vertical element physically connects to a bottom surface of each of the horizontal elements, and the second vertical element misaligns the first vertical element. The present invention also provides an electric connector including a first vertical element and a second vertical element. The first vertical element physically connects to a top surface of a horizontal element. The second vertical element physically connects to a bottom surface of the horizontal element, and the second vertical element misaligns the first vertical element, wherein the first vertical element or the horizontal element is burned out before the second vertical element is burned out while a voltage is applied.

公开(公告)号：US09786654B1

公开(公告)日：2017-10-10

申请号：US15298248

申请日：2016-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/87

Abstract: An ESD protection semiconductor device includes a substrate, a first isolation structure disposed in the substrate, a gate disposed on the substrate and overlapping a portion of the first isolation structure, a source region formed in the substrate at a first side of the gate, and a drain region formed in the substrate at a second side of the gate opposite to the first side. The substrate and the drain region include a first conductivity type, the source region includes a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other.

公开(公告)号：US20170194314A1

公开(公告)日：2017-07-06

申请号：US15007163

申请日：2016-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wei Lee ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/7436 ,  H01L29/861

Abstract: An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.

公开(公告)号：US09607977B1

公开(公告)日：2017-03-28

申请号：US14920902

申请日：2015-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8249 ,  H01L21/8234

CPC classification number: H01L21/823475 ,  H01L21/8249 ,  H01L27/027 ,  H01L29/1095 ,  H01L29/78 ,  H01L29/7816

Abstract: An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The anode is coupled to an input terminal, and the cathode is coupled to a ground. The negative voltage holding transistor includes an N-well. The positive voltage holding transistor includes an N-well. The N-well of the positive voltage holding transistor and the N-well of the negative voltage holding transistor are coupled together and are float. The negative voltage holding transistor and the positive voltage holding transistor are coupled between the anode and the cathode in a manner of back-to-back.

公开(公告)号：US20160293593A1

公开(公告)日：2016-10-06

申请号：US14691126

申请日：2015-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Yi-Chun Chen ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10

CPC classification number: H01L27/0266 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36

Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.

Abstract translation: 半导体结构包括阱，第一轻掺杂区，第二轻掺杂区，第一重掺杂区，第二重掺杂区和栅极。 第一轻掺杂区域设置在阱中。 第二轻掺杂区域设置在阱中并与第一轻掺杂区域分离。 第一重掺杂区域设置在第一轻掺杂区域中。 第二重掺杂区域部分地设置在第二轻掺杂区域中。 第二重掺杂区域具有接触阱的表面。 栅极设置在第一重掺杂区域和第二重掺杂区域之间的阱上。 该井具有第一种掺杂型。 第一轻掺杂区域，第二轻掺杂区域，第一重掺杂区域和第二重掺杂区域具有第二掺杂类型。

公开(公告)号：US09972615B1

公开(公告)日：2018-05-15

申请号：US15351413

申请日：2016-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7835

Abstract: A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. The first doped region is disposed in a second doped well at a second side of the gate and has a second conductivity type. The source region is also disposed in the second doped well and has the first conductive type, and the source region surrounds the first doped region from a topview. The second doped region is disposed in the second doped well and has the second conductive type, and the second doped region is disposed between the gate and the source region, wherein a plurality of contacts is electrically connected to the second doped region.

公开(公告)号：US20170323880A1

公开(公告)日：2017-11-09

申请号：US15188962

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yu Tai ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0277 ,  H01L29/0623 ,  H01L29/0653

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and has a second conductive type. The source region is disposed in the doped well and has the second conductive type, wherein the source region is separated from the drain region. The doped region is disposed in the doped well between the drain region and the source region, wherein the doped region has the first conductive type and is in contact with the doped well and the source region. The guard ring is disposed in the doped well and has the first conductive type.

公开(公告)号：US09607980B1

公开(公告)日：2017-03-28

申请号：US15011681

申请日：2016-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7826

Abstract: The present invention provides a high voltage transistor including a substrate, a first base region having a first conductivity type, and a first doped region, a second doped region, a second base region and a third doped region having a second conductivity type complementary to the first conductivity type. The first base region, the second doped region, the second base region and the third doped region are disposed in the substrate, and the first doped region is disposed in the substrate. The third doped region, the second base region and the second doped region are stacked sequentially, and the doping concentrations of the third doped region, the second base region and the second doped region gradually increase.

公开(公告)号：US20160204598A1

公开(公告)日：2016-07-14

申请号：US14594173

申请日：2015-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H02H9/04

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0288 ,  H02H9/046

Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

Abstract translation: 本发明提供一种电连接在高压电力线和低电压电力线之间的ESD保护电路，该ESD保护电路包括双极结型晶体管（BJT）和触发源。 BJT的集电极电连接到高压电力线，并且BJT的发射极和基极电连接到低压电力线。 触发源电连接在BJT的基极和高压电源线之间。