公开(公告)号：US12206020B2

公开(公告)日：2025-01-21

申请号：US18139964

申请日：2023-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US12002883B2

公开(公告)日：2024-06-04

申请号：US17578383

申请日：2022-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Che-Hua Chang

IPC: H01L29/786 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L29/78618 ,  H01L29/7869

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.

公开(公告)号：US20230231033A1

公开(公告)日：2023-07-20

申请号：US18125136

申请日：2023-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/76224 ,  H01L21/0223 ,  H01L21/2652

Abstract: The invention provides a manufacturing method of a semiconductor structure, the method includes providing a substrate, forming two shallow trench isolation structures in the substrate. A first region, a second region and a third region are defined between the two shallow trench isolation structures, and the second region is located between the first region and the third region. Next, an oxide layer is formed in the first region, the second region and the third region, and the oxide layer directly contacts the two shallow trench isolation structures. The oxide layer in the second region is then removed, and another oxide layer is formed in the first region, the second region and the third region, so that a thick oxide layer is formed in the first and third regions, and a thin oxide layer is formed in the second region.

公开(公告)号：US20230215914A1

公开(公告)日：2023-07-06

申请号：US17577386

申请日：2022-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/7816 ,  H01L29/0692 ,  H01L29/7835

Abstract: A semiconductor high-voltage device includes a semiconductor substrate; a high-voltage well in the semiconductor substrate; a drift region in the high-voltage well; a recessed channel region adjacent to the drift region; a heavily doped drain region in the drift region and spaced apart from the recessed channel; an isolation structure between the recessed channel region and the heavily doped drain region in the drift region; a buried gate dielectric layer on the recessed channel region, wherein the top surface of the buried gate dielectric layer is lower than the top surface of the heavily doped drain region; and a gate on the buried gate dielectric layer.

公开(公告)号：US20230163128A1

公开(公告)日：2023-05-25

申请号：US17556972

申请日：2021-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/7869 ,  H01L21/02565 ,  H01L21/8258 ,  H01L29/66969

Abstract: The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.

公开(公告)号：US20220209009A1

公开(公告)日：2022-06-30

申请号：US17159166

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US11101381B2

公开(公告)日：2021-08-24

申请号：US16601364

申请日：2019-10-14

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: A structure of a high voltage transistor includes a substrate. A gate insulating layer is disposed on the substrate. A shallow trench isolation structure is formed in the substrate adjacent to the gate insulating layer. The shallow trench isolation structure includes a first sidewall and a second sidewall. A top portion of the first sidewall merges with a side region of the gate insulating layer. A bottom surface of the shallow trench isolation structure is gradually decreasing in depth from the second sidewall to the first sidewall. A source/drain region is formed in the substrate at a side of the gate insulating layer and surrounding the shallow trench isolation structure.

公开(公告)号：US20210167208A1

公开(公告)日：2021-06-03

申请号：US16711442

申请日：2019-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Shin-Hung Li

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A semiconductor transistor includes a first lightly doped-drain region disposed in a drain region of a semiconductor substrate; a first heavily doped region disposed in the first lightly doped-drain region; and a gate located on the channel region; a gate oxide layer between the gate and the channel region; and a first insulating feature disposed in the first lightly doped-drain region between the channel region and the first heavily doped region. The gate overlaps with the first insulating feature. The thickness of the first insulating feature is greater than that of the gate oxide layer.

公开(公告)号：US12261202B2

公开(公告)日：2025-03-25

申请号：US17577386

申请日：2022-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor high-voltage device includes a semiconductor substrate; a high-voltage well in the semiconductor substrate; a drift region in the high-voltage well; a recessed channel region adjacent to the drift region; a heavily doped drain region in the drift region and spaced apart from the recessed channel; an isolation structure between the recessed channel region and the heavily doped drain region in the drift region; a buried gate dielectric layer on the recessed channel region, wherein the top surface of the buried gate dielectric layer is lower than the top surface of the heavily doped drain region; and a gate on the buried gate dielectric layer.

公开(公告)号：US20250072221A1

公开(公告)日：2025-02-27

申请号：US18466855

申请日：2023-09-14

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li

IPC: H10K59/122 ,  H01L21/311 ,  H10K59/173 ,  H10K71/60

Abstract: A manufacturing method of a semiconductor structure including the following steps is disclosed. A definition layer is formed on a substrate. The definition layer includes a first dielectric layer and a second dielectric layer. A first isotropic etching process is performed on the second dielectric layer to form a first opening in the second dielectric layer. A portion of the first opening is located under the patterned photoresist layer. A first anisotropic etching process is performed on the first dielectric layer to form a second opening in the first dielectric layer. The first opening is connected to the second opening to form a third opening. The patterned photoresist layer is removed. An etch back process is performed on the first dielectric layer and the second dielectric layer, so that a sidewall of the definition layer exposed by the third opening is an inclined surface.