公开(公告)号：US09691733B1

公开(公告)日：2017-06-27

申请号：US15221609

申请日：2016-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xu Yang Shen ,  Sin-Shien Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/0504

Abstract: A bonded semiconductor structure includes a first substrate and a second substrate. The first substrate includes a first interconnection structure, a first dielectric layer, and a first silicon carbon nitride (SiCN) layer sequentially stacked thereon. And at least a first conductive pad is formed in the first dielectric layer and the first SiCN layer. The second substrate includes a second interconnection structure, a second dielectric layer, and a second SiCN layer sequentially stacked thereon. And at least a second conductive pad is formed in the second dielectric layer and the second SiCN layer. The first conductive pad physically contacts the second conductive pad, and the first SiCN layer physically contacts the second SiCN layer.

公开(公告)号：US20160268230A1

公开(公告)日：2016-09-15

申请号：US14656704

申请日：2015-03-12

Applicant: United Microelectronics Corp.

Inventor： Sin-Shien Lin ,  Fei Wang ,  Chien-En Hsu

IPC: H01L25/065 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53295 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80097 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: A stacked semiconductor structure includes a first wafer, a second wafer, a first insulting layer, and a second insulating layer. The first wafer includes a first front surface, a first back surface, and a first interconnection structure. The first interconnection structure includes at least a first top metal layer exposed on the first front surface of the first wafer. The second wafer includes a second front surface, a second back surface, and a second interconnection structure. The second interconnection structure includes at least a second top metal layer exposed on the second front surface of the second wafer. The first insulating layer is formed on the first front surface of the first wafer, and the second insulating layer is formed on the second front surface of the second wafer. The first insulating layer and the second insulating layer contact each other.

Abstract translation: 叠层半导体结构包括第一晶片，第二晶片，第一绝缘层和第二绝缘层。 第一晶片包括第一前表面，第一后表面和第一互连结构。 第一互连结构包括暴露在第一晶片的第一前表面上的至少第一顶金属层。 第二晶片包括第二前表面，第二后表面和第二互连结构。 第二互连结构包括暴露在第二晶片的第二前表面上的至少第二顶金属层。 第一绝缘层形成在第一晶片的第一前表面上，第二绝缘层形成在第二晶片的第二前表面上。 第一绝缘层和第二绝缘层彼此接触。