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    Manufacturing method of capacitor structure
    1.
    发明授权
    Manufacturing method of capacitor structure 有权

    公开(公告)号：US11024704B1

    公开(公告)日：2021-06-01

    申请号：US16802481

    申请日：2020-02-26

    Applicant: United Semiconductor (Xiamen) Co., Ltd.

    Inventor： Wei-Chun Chang ,  Han-Min Huang ,  You-Di Jhang ,  Wen Yi Tan

    IPC: H01G7/00 ,  H01G4/00 ,  H01G4/30 ,  H01G4/38 ,  H01L49/02

    Abstract: A manufacturing method of a capacitor structure includes the following steps. A first capacitor is formed on a substrate. The first capacitor includes a first electrically conductive pattern and a second electrically conductive pattern of a first electrically conductive layer and a first dielectric layer disposed therebetween in a horizontal direction. A second capacitor is formed on the substrate before forming the first capacitor. The second capacitor includes a third electrically conductive pattern and a fourth electrically conductive pattern of a second electrically conductive layer and a second dielectric layer disposed therebetween in the horizontal direction. A thickness of the second electrically conductive layer is monitored. A target value of a thickness of the first electrically conductive layer is controlled in accordance with a value of a monitored thickness of the second electrically conductive layer.

    METHOD OF FABRICATING INTEGRATED CIRCUIT
    2.
    发明申请
    METHOD OF FABRICATING INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20200266237A1

    公开(公告)日：2020-08-20

    申请号：US16868495

    申请日：2020-05-06

    Applicant: United Semiconductor (Xiamen) Co., Ltd.

    Inventor： Chin-Chun Huang ,  Yun-Pin Teng ,  You-Di Jhang ,  WEN YI TAN

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

    Integrated circuit including resistive random-access memory cell and resistor cell and forming method thereof
    3.
    发明授权
    Integrated circuit including resistive random-access memory cell and resistor cell and forming method thereof 有权

    公开(公告)号：US10692929B1

    公开(公告)日：2020-06-23

    申请号：US16231615

    申请日：2018-12-24

    Applicant: United Semiconductor (Xiamen) Co., Ltd.

    Inventor： Chin-Chun Huang ,  Yun-Pin Teng ,  You-Di Jhang ,  Wen Yi Tan

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

    Method of fabricating integrated circuit
    6.
    发明授权
    Method of fabricating integrated circuit 有权

    公开(公告)号：US10937830B2

    公开(公告)日：2021-03-02

    申请号：US16868495

    申请日：2020-05-06

    Applicant: United Semiconductor (Xiamen) Co., Ltd.

    Inventor： Chin-Chun Huang ,  Yun-Pin Teng ,  You-Di Jhang ,  Wen Yi Tan

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

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