公开(公告)号：US12199150B2

公开(公告)日：2025-01-14

申请号：US17848422

申请日：2022-06-24

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun Zhou ,  Jianwen Cao ,  Yue Shi ,  Bo Zhang

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

公开(公告)号：US10862463B1

公开(公告)日：2020-12-08

申请号：US16848864

申请日：2020-04-15

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun Zhou ,  Jianwen Cao ,  Zhuo Wang ,  He Tang ,  Bo Zhang

IPC: H03K19/0185 ,  H03K3/356 ,  H03K3/012 ,  H03K5/134

Abstract: A level shifter includes a power supply rail conversion block, an RS latch and a digital detection block. The power supply rail conversion block comprises a first NLDMOS transistor, a second NLDMOS transistor, a first PLDMOS transistor, a second PLDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first inverter. A gate of the first NLDMOS transistor is connected to an input of the first inverter, a drain of the first NLDMOS transistor is connected to a drain of the first PLDMOS transistor; a source of the first NLDMOS transistor and a source of the second NLDMOS are connected to a referenced ground of an LV power supply rail. The digital detection block comprises a second inverter, a third inverter, a first delay chain, a second delay chain, a first NAND gate and a second NAND gate.

公开(公告)号：US10146238B2

公开(公告)日：2018-12-04

申请号：US15599484

申请日：2017-05-19

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun Zhou ,  Yao Wang ,  Jianwen Cao ,  Hongming Yu ,  Yunkun Wang ,  Anqi Wang ,  Zhuo Wang ,  Bo Zhang

IPC: G05F1/10 ,  G05F3/02 ,  G05F1/46 ,  G05F3/24 ,  G05F3/16 ,  H02J7/00

Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to μT2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of −40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from μW level to nW level and realize low power consumption.