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    Host controller of high-speed data interface with clock-domain crossing
    1.
    发明授权
    Host controller of high-speed data interface with clock-domain crossing 有权

    公开(公告)号：US10042810B2

    公开(公告)日：2018-08-07

    申请号：US15171362

    申请日：2016-06-02

    Applicant: VIA Alliance Semiconductor Co., Ltd.

    Inventor： Wanfeng Wang ,  Xiaoliang Ji ,  Zhiqiang Hui ,  Huiying Hou

    IPC: G06F13/42

    Abstract: A host controller with suppressed data jitter is shown, which uses a logical physical layer (LPHY) to provide groups of low-speed data, uses a clock-domain-crossing transmitter (TXCDC) to transmit the groups of the low-speed data to the corresponding electrical physical layers (EPHYs), uses the EPHYs to convert the groups of the low-speed data to high-speed data and transmit the high-speed data to the corresponding external devices, and further has a multiplexer. Each EPHY corresponds to one clock signal and operates accordingly. The multiplexer receives the clock signals of the EPHYs to output a common clock signal for the LPHY to provide the groups of low-speed data and for the TXCDC to retrieve the groups of low-speed data. With respect to each of the external devices, the TXCDC uses the clock signal corresponding to the corresponding EPHY to output the corresponding group of low-speed data to the corresponding EPHY.

    Peripheral interface circuit at host side and electronic system using the same
    3.
    发明授权
    Peripheral interface circuit at host side and electronic system using the same 有权

    公开(公告)号：US09804634B2

    公开(公告)日：2017-10-31

    申请号：US14589189

    申请日：2015-01-05

    Applicant: VIA Alliance Semiconductor Co., Ltd.

    Inventor： Zhiqiang Hui ,  Lingyan Zhong ,  Yunxing Dong

    IPC: G06F13/42 ,  G06F1/12

    CPC classification number: G06F1/12 ,  G06F13/4226 ,  G06F13/4291

    Abstract: A peripheral interface circuit at host side and an electronic system using the same is disclosed. The peripheral interface circuit has a bus clock signal generator and a data register. The bus clock signal generator outputs a bus clock signal based on a host clock signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data. The data register receives the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. The bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal.

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