公开(公告)号：US12132408B2

公开(公告)日：2024-10-29

申请号：US17819353

申请日：2022-08-12

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Yuliang Cao ,  Dong Dong

IPC: H02M3/335 ,  H02M1/088 ,  H02M3/00

CPC classification number: H02M3/33584 ,  H02M1/088 ,  H02M3/01 ,  H02M3/33576 ,  H02M3/33592

Abstract: Power converters including electronic-embedded transformers for current sharing and load-independent voltage gain are described. In one example, a power converter system includes an input, an output, a power converter between the input and output, and a controller. The converter includes a first bridge, a second bridge, and an electronic-embedded transformer (EET) between the first and second bridge. The EET includes a capacitor and a capacitance coupling switch bridge. The controller generates switching control signals for the first and second bridges and phasing drive control signals for the capacitance coupling switch bridge in the EET. The controller applies a phase shift to the phasing drive control signals for the EET as compared to the switching control signals for the first and second bridges, so that the voltage across the capacitor in the EET cancels the leakage inductance of the transformer windings in the EET, at any switching frequency.

公开(公告)号：US11552549B2

公开(公告)日：2023-01-10

申请号：US17064080

申请日：2020-10-06

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Xiang Lin ,  Dong Dong ,  Rolando Burgos

IPC: H02M1/08 ,  H02M1/00

Abstract: A voltage balancing circuit for use in a power converter is described. In one example, a power converter includes series-connected switching transistors for power conversion, and a voltage balancing control loop. The voltage balancing control loop includes a measurement circuit electrically coupled to a transistor in the pair of series-connected switching transistors. The measurement circuit is electrically coupled to measure a body voltage reference of the transistor. The voltage balancing control loop also includes a balancing circuit configured to generate a balancing pulse signal for adjusting a voltage across the transistor using the body voltage reference, and a circuit configured to combine the balancing pulse signal with a gate drive pulse signal for the transistor, to form a balanced gate drive pulse signal for the transistor. The balanced gate drive pulse signal helps to equalize the body diode voltages of the series-connected switching transistors, particularly during “off” periods.

公开(公告)号：US20240097572A1

公开(公告)日：2024-03-21

申请号：US17932399

申请日：2022-09-15

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Yuliang Cao ,  Yijie Bai ,  Vladimir Mitrovic ,  Boran Fan ,  Dong Dong ,  Rolando Burgos

IPC: H02M3/335 ,  H02M1/08

CPC classification number: H02M3/33573 ,  H02M1/08

Abstract: Power systems including converters that exhibit reduced common mode voltage emissions are described. In one example, a power converter system includes an input and an output, a multi-level switch bridge coupled between the input and the output, an input capacitor branch coupled across the input, an output capacitor branch coupled across the output, and a controller configured to generate switching control signals for the multi-level buck-boost switch bridge. The multi-level switch bridge also includes a plurality of inductors in one example. In one case, a quadrangular or quadrangle control mode can be relied upon to switch the multi-level switch bridge, to minimize the ripple in the inductors, achieve zero voltage switching, reduce common mode electromagnetic interference emission by the converter, and for other benefits.

公开(公告)号：US11515807B1

公开(公告)日：2022-11-29

申请号：US17477678

申请日：2021-09-17

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Jian Liu ,  Dong Dong

IPC: H02M7/42 ,  H02M7/483 ,  H02M7/5387

Abstract: Aspects are described for line frequency commutated voltage source converters for multiphase modular multilevel converters. A voltage source converter (VSC) capacitor voltage of a multiphase VSC of a multiphase power converter can be identified. The multiphase VSC can include a half-bridge circuit for each phase of the multiphase power converter. A circuit parameter can be identified and utilized to determine an arm voltage of an arm of a branch of the multiphase converter. Switch control signals can be generated to insert or bypass the VSC capacitor for the arm of the branch of the multiphase converter device, based at least in part on a comparison between the arm voltage and the VSC capacitor voltage.

公开(公告)号：US20220069719A1

公开(公告)日：2022-03-03

申请号：US17008893

申请日：2020-09-01

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Yuliang Cao ,  Minh Ngo ,  Ning Yan ,  Dong Dong ,  Rolando Burgos

IPC: H02M3/335 ,  H02M7/5387

Abstract: Aspects of bidirectional architectures with partial energy processing in resonant direct current (DC)-to-DC converters are described. In one embodiment, an alternating circuit (AC)-to-DC circuit generates an AC voltage from a DC voltage. A voltage of the AC voltage is transformed into a majority AC voltage of a majority power path and at least one minority AC voltage of the minority power paths. The majority AC voltage is rectified into a majority DC voltage and a minority AC voltage is rectified into a minority DC voltage. The majority power path and the minority power path are combined as a combined DC voltage.

公开(公告)号：US08957666B2

公开(公告)日：2015-02-17

申请号：US13910371

申请日：2013-06-05

Applicant: Virginia Tech Intellectual Properties, Inc.

Inventor： Dong Dong ,  Dushan Boroyevich ,  Paolo Mattavelli ,  Bo Wen

IPC: G01R23/12 ,  G01R23/00 ,  H03L7/08

CPC classification number: H03L7/08 ,  G01R31/42 ,  H02J3/382 ,  H02J2003/388

Abstract: A small signal feedback loop or feed-forward loop having gain provides substantially unconditional instability in a phase locked loop when a reference phase signal is lost. The small signal feedback or feed-forward also modifies phase locked loop bandwidth when the reference phase signal is lost to increase rapidity of response to loss of reference phase signal while maintaining insensitivity to reference voltage amplitude change while the reference phase signal is present. The performance thus achieved is particularly suitable for rapid condition detection response and control of a grid connected power converter under islanding conditions.

Abstract translation: 当参考相位信号丢失时，具有增益的小信号反馈回路或前馈回路在锁相环中提供基本上无条件的不稳定性。 当参考相位信号丢失时，小信号反馈或前馈也会修改锁相环带宽，以增加对参考相位信号丢失的响应速度，同时在参考相位信号存在的同时保持对参考电压幅度变化的不敏感性。 这样实现的性能特别适用于孤岛状态下并网功率转换器的快速状态检测响应和控制。

公开(公告)号：US20220109363A1

公开(公告)日：2022-04-07

申请号：US17064080

申请日：2020-10-06

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Xiang Lin ,  Dong Dong ,  Rolando Burgos

IPC: H02M1/08

Abstract: A voltage balancing circuit for use in a power converter is described. In one example, a power converter includes series-connected switching transistors for power conversion, and a voltage balancing control loop. The voltage balancing control loop includes a measurement circuit electrically coupled to a transistor in the pair of series-connected switching transistors. The measurement circuit is electrically coupled to measure a body voltage reference of the transistor. The voltage balancing control loop also includes a balancing circuit configured to generate a balancing pulse signal for adjusting a voltage across the transistor using the body voltage reference, and a circuit configured to combine the balancing pulse signal with a gate drive pulse signal for the transistor, to form a balanced gate drive pulse signal for the transistor. The balanced gate drive pulse signal helps to equalize the body diode voltages of the series-connected switching transistors, particularly during “off” periods.

公开(公告)号：US11271492B2

公开(公告)日：2022-03-08

申请号：US16939914

申请日：2020-07-27

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Lakshmi Ravi ,  Joshua Stewart ,  Dong Dong ,  Rolando Burgos

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H02M7/00

Abstract: An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.

公开(公告)号：US20220029549A1

公开(公告)日：2022-01-27

申请号：US16939914

申请日：2020-07-27

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Lakshmi Ravi ,  Joshua Stewart ,  Dong Dong ,  Rolando Burgos

IPC: H02M7/00 ,  H05K1/02 ,  H05K1/11

Abstract: An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.

公开(公告)号：US09634673B2

公开(公告)日：2017-04-25

申请号：US13968487

申请日：2013-08-16

Applicant: Virginia Tech Intellectual Properties, Inc.

Inventor： Dong Dong ,  Dushan Boroyevich ,  Paolo Mattavelli

IPC: H03L7/08 ,  H02J3/38

CPC classification number: H03L7/08 ,  H02J3/38 ,  H02J2003/388

Abstract: Wobbling the operating frequency of a phase-locked loop (PLL), preferably by adding a periodic variation is feedback gain or delay in reference signal phase allows the avoidance of any non-detection zone that might occur due to exact synchronization of the phase locked loop operating frequency with a reference signal. If the change in PLL operating frequency is periodic, it can be made of adequate speed variation to accommodate and time requirement for islanding detection or the like when a reference signal being tracked by the PLL is lost. Such wobbling of the PLL operating frequency is preferably achieved by addition a periodic variable gain in a feedback loop and/or adding a periodically varying phase delay in a reference signal and/or PLL output.