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公开(公告)号：US08797080B2
公开(公告)日：2014-08-05
申请号：US13619859
申请日：2012-09-14
IPC分类号： H03H11/26
CPC分类号： H03L7/0802 , G11C7/04 , G11C7/222 , H03K5/159 , H03L7/08 , H03L7/0816
摘要： Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.
摘要翻译： 公开延迟模型的电路，装置和方法。 在一个这样的示例电路中，第一延迟模型电路被配置为通过对通过路径的信号的延迟进行建模来提供第一输出信号。 第二延迟模型电路被配置为通过对通过路径的信号的延迟进行建模来提供第二输出信号。 比较电路耦合到第一和第二延迟模型电路。 比较电路被配置为比较来自第一延迟模型电路的第三信号和来自第二延迟模型电路的第四信号，并且响应于提供调整信号以调整第二延迟模型电路的延迟。
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公开(公告)号：US20140077851A1
公开(公告)日：2014-03-20
申请号：US13619859
申请日：2012-09-14
IPC分类号： H03L7/097
CPC分类号： H03L7/0802 , G11C7/04 , G11C7/222 , H03K5/159 , H03L7/08 , H03L7/0816
摘要： Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.
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3.发明授权公开(公告)号：US08441888B2
公开(公告)日：2013-05-14
申请号：US13149435
申请日：2011-05-31
IPC分类号： G11C8/00
CPC分类号： G11C7/10 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2272
摘要： Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.
摘要翻译： 用于锁存写命令的电路，存储器和方法，并且稍后提供包括写命令和写数据定时电路的写数据。 一个这样的定时电路包括内部写入命令锁存器，以响应写入命令锁存信号来锁存内部写入命令。 在延迟延迟之后，内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。 定时电路还包括写平均触发器（FF）电路和写数据寄存器。 一种这样的方法包括产生和锁定内部写命令。 锁存的内部写入命令在响应于存储器时钟信号的延迟延迟之后被释放。 内部写入命令通过内部写命令路径进行传播。 写数据被捕获，并且内部写命令响应于写时钟信号而被锁存。 捕获的写入数据被释放以写入存储器。
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公开(公告)号：US20110298494A1
公开(公告)日：2011-12-08
申请号：US13210914
申请日：2011-08-16
IPC分类号： H03K19/094
CPC分类号： H03K19/01721
摘要： Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry that provide voltages to thin-gate dielectric transistors. One such buffer may include a primary pull-up pre-driver operably coupled to a primary pull-up transistor; a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor; a primary pull-down pre-driver operably coupled to a primary pull-down transistor; and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. The pre-drivers may provide a sufficiently low voltage to a gate of a transistor operably coupled thereto so as to sustain a gate dielectric integrity of the transistor, wherein at least one of the primary pull-up pre-driver, the secondary pull-up pre-driver, primary pull-down pre-driver, and the secondary pull-down pre-driver is configured to provide a voltage greater than or equal to a ground voltage and less than or equal to a supply voltage.
摘要翻译： 公开了方法，装置和系统，包括用于具有向薄栅极介质晶体管提供电压的预驱动器电路的缓冲器。 一个这样的缓冲器可以包括可操作地耦合到初级上拉晶体管的初级上拉预驱动器; 可操作地耦合到次级上拉晶体管的次级上拉预驱动器; 可操作地耦合到初级下拉晶体管的主下拉预驱动器; 以及可操作地耦合到次级下拉晶体管的次级下拉预驱动器。 预驱动器可以向可操作地耦合到其的晶体管的栅极提供足够低的电压，以便维持晶体管的栅极电介质完整性，其中初级上拉预驱动器，次级上拉电路中的至少一个 预驱动器，主下拉预驱动器和辅助下拉预驱动器被配置为提供大于或等于接地电压并小于或等于电源电压的电压。
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公开(公告)号：US08004313B2
公开(公告)日：2011-08-23
申请号：US12577506
申请日：2009-10-12
IPC分类号： H03K19/0175
CPC分类号： H03K19/01721
摘要： Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality of pre-drivers is operably coupled to a transistor of a plurality of transistors. The buffer may further comprise one or more clamping devices, wherein at least one transistor of the plurality of transistors has a gate coupled to at least one clamping device of the one or more clamping devices.
摘要翻译： 公开了方法，装置和系统，包括用于具有被配置为向薄栅介质晶体管提供电压的预驱动器电路的缓冲器。 一个这样的缓冲器可以包括多个预驱动器，其中多个预驱动器中的每个预驱动器可操作地耦合到多个晶体管的晶体管。 缓冲器还可以包括一个或多个钳位装置，其中多个晶体管中的至少一个晶体管具有耦合到一个或多个钳位装置的至少一个夹持装置的栅极。
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6.发明授权公开(公告)号：US07969813B2
公开(公告)日：2011-06-28
申请号：US12416761
申请日：2009-04-01
IPC分类号： G11C8/00
CPC分类号： G11C7/10 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2272
摘要： Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.
摘要翻译： 用于锁存写命令的电路，存储器和方法，并且稍后提供包括写命令和写数据定时电路的写数据。 一个这样的定时电路包括内部写入命令锁存器，以响应写入命令锁存信号来锁存内部写入命令。 在延迟延迟之后，内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。 定时电路还包括写平均触发器（FF）电路和写数据寄存器。 一种这样的方法包括产生和锁定内部写命令。 锁存的内部写入命令在响应于存储器时钟信号的延迟延迟之后被释放。 内部写入命令通过内部写命令路径进行传播。 写数据被捕获，并且内部写命令响应于写时钟信号而被锁存。 捕获的写入数据被释放以写入存储器。
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7.发明申请公开(公告)号：US20110228625A1
公开(公告)日：2011-09-22
申请号：US13149435
申请日：2011-05-31
IPC分类号： G11C8/18
CPC分类号： G11C7/10 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2272
摘要： Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.
摘要翻译： 用于锁存写命令的电路，存储器和方法，并且稍后提供包括写命令和写数据定时电路的写数据。 一个这样的定时电路包括内部写入命令锁存器，以响应写入命令锁存信号来锁存内部写入命令。 在延迟延迟之后，内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。 定时电路还包括写平均触发器（FF）电路和写数据寄存器。 一种这样的方法包括产生和锁定内部写命令。 锁存的内部写入命令在响应于存储器时钟信号的延迟延迟之后被释放。 内部写入命令通过内部写命令路径进行传播。 写数据被捕获，并且内部写命令响应于写时钟信号而被锁存。 捕获的写入数据被释放以写入存储器。
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公开(公告)号：US20100208533A1
公开(公告)日：2010-08-19
申请号：US12771578
申请日：2010-04-30
CPC分类号： G11C8/18 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.
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9.发明申请公开(公告)号：US20100054058A1
公开(公告)日：2010-03-04
申请号：US12203533
申请日：2008-09-03
CPC分类号： G11C8/18 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.
摘要翻译： 本发明的实施例包括使用系统时钟和写时钟将地址和数据信号发送到存储器阵列的电路。 可以使用锁定环来补偿系统时钟相对于写入时钟所经历的附加延迟并确保时钟信号的同步。 可以使用写锁存器使能块来产生用于发出的写锁存器使能信号以及相应的地址信号。 写锁存器使能信号可以被定时使得其到达适当的时间以发出对应于发出的地址的数据。
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公开(公告)号：US20090108871A1
公开(公告)日：2009-04-30
申请号：US11877868
申请日：2007-10-24
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/01721
摘要： Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors One such buffer may comprise a primary pull-up pre-driver operably coupled to a primary pull-up transistor, a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor, a primary pull-down pre-driver operably coupled to a primary pull-down transistor, and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. Each of the primary pull-up pre-driver, the secondary pull-up pre-driver., primary pull-down pre-driver, and the secondary pull-down pre-driver are configured to provide a voltage to a gate of a transistor operably coupled thereto at a voltage level so as to sustain gate dielectric integrity of the transistor.
摘要翻译： 公开了方法，装置和系统，包括用于具有配置为向薄栅介质晶体管提供电压的预驱动器电路的缓冲器。一个这样的缓冲器可以包括可操作地耦合到初级上拉的初级上拉预驱动器 晶体管，可操作地耦合到次级上拉晶体管的次级上拉预驱动器，可操作地耦合到初级下拉晶体管的初级下拉预驱动器，以及可操作地耦合到 次级下拉晶体管。 初级上拉预驱动器，次级上拉预驱动器，初级下拉预驱动器和次级下拉预驱动器中的每一个被配置为向晶体管的栅极提供电压 以电压电平可操作地耦合到其，以便维持晶体管的栅极电介质完整性。
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