公开(公告)号：US06963111B2

公开(公告)日：2005-11-08

申请号：US10460974

申请日：2003-06-13

申请人： Vijay K. Reddy ,  Gianluca Boselli ,  Ekanayake A. Amerasekera

发明人： Vijay K. Reddy ,  Gianluca Boselli ,  Ekanayake A. Amerasekera

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/76

CPC分类号： H01L27/0277

摘要： A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.

摘要翻译： pMOS晶体管（601）位于n阱（602）中并且具有至少一个栅极（603）。 晶体管（601）连接在电源焊盘Vdd或I / O焊盘（604）和地电位Vss（605）之间。 门（603）连接到电源垫（604）。 n阱（602）电容（620）耦合到地（605），与晶体管源（606）分离并在正常工作条件下浮置。 在ESD事件下，由源极（606）和n阱（602）形成的二极管被正向偏置（n阱负偏置），以接通横向pnp晶体管以放电ESD电流。 阱电压持续增加直到触发横向双极pnp晶体管的值。 ESD保护可以通过栅极（603）的宽度扩展，随着栅极宽度的缩小而提高。

公开(公告)号：US09035352B2

公开(公告)日：2015-05-19

申请号：US13459504

申请日：2012-04-30

申请人： Gianluca Boselli ,  Rajkumar Sankaralingam

发明人： Gianluca Boselli ,  Rajkumar Sankaralingam

IPC分类号： H01L29/66 ,  H01L29/74 ,  H01L27/02 ,  H01L23/62

CPC分类号： H01L29/7436 ,  H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.

摘要翻译： LSCR包括具有p掺杂的半导体表面的衬底。 彼此隔开的第一nwell和第二nwell是横向间隔距离在半导体表面中。 第一n +扩散区域和第一p +扩散区域处于第一n阱。 第二个n +扩散区处于第二个nwell。 第二p +扩散在第一nwell和第二nwell之间，其提供与半导体表面的接触。 电介质隔离位于第一n +扩散区和第一p +扩散区之间，沿着第一n阱和半导体表面之间的周边，以及第二n阱和半导体表面之间的周边。 电阻器提供第二n +扩散区和第二p +扩散之间的耦合。

公开(公告)号：US08589839B2

公开(公告)日：2013-11-19

申请号：US12506597

申请日：2009-07-21

申请人： Gianluca Boselli ,  Jonathan S. Brodsky ,  John E. Kunz, Jr.

发明人： Gianluca Boselli ,  Jonathan S. Brodsky ,  John E. Kunz, Jr.

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H01L27/0248

摘要： Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.

摘要翻译： 公开了一种静电放电（ESD）保护验证器，一种用于对IC和ESD验证系统进行ESD保护的验证方法。 在一个实施例中，ESD保护验证器包括：（1）电路分析器，被配置为将IC的组件信息与预定义的ESD保护元件进行比较，以识别IC的ESD单元;以及（2）ESD单元验证器，被配置为将相关的物理属性 将所识别的ESD电池与ESD保护要求相结合，并确定其符合性。

公开(公告)号：US07282767B2

公开(公告)日：2007-10-16

申请号：US11155062

申请日：2005-06-17

申请人： Charvaka Duvvury ,  Gianluca Boselli ,  John E. Kunz, Jr.

发明人： Charvaka Duvvury ,  Gianluca Boselli ,  John E. Kunz, Jr.

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0619

摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction 512c. Source 512 has further an ohmic (silicided) connection to contact 513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有与第一n阱的指状接触（513），其接触源极结512c。 源512还具有与触点513的欧姆（硅化）连接。 具有其阴极（521）的指状二极管（520）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到功率（Vdd）并且大致垂直于第一n阱接触，用作保护壁 （550）。

公开(公告)号：US07196887B2

公开(公告)日：2007-03-27

申请号：US10446369

申请日：2003-05-28

申请人： Gianluca Boselli ,  Vijay Kumar Reddy ,  Ekanayake Ajith Amerasekera

发明人： Gianluca Boselli ,  Vijay Kumar Reddy ,  Ekanayake Ajith Amerasekera

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L29/7833

摘要： A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.

摘要翻译： 公开了一种PMOS ESD保护器件，其中实施栅极和衬底耦合技术以在正ESD事件期间提供保护。 去除能够根据本发明的一个或多个方面产生的曲线中的快速回转支腿，从而减小了装置导通的触发电压，以便小于对应于第二击穿的第二电压 地区。

公开(公告)号：US07145204B2

公开(公告)日：2006-12-05

申请号：US11107033

申请日：2005-04-15

申请人： Charvaka Duvvury ,  Gianluca Boselli ,  John E. Kunz, Jr.

发明人： Charvaka Duvvury ,  Gianluca Boselli ,  John E. Kunz, Jr.

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0619

摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well. Further a finger-shaped diode (520) with its cathode (521) located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有到第一n阱的手指形状的接触（513）。 此外，指状二极管（520），其阴极（521）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到地面并且大致垂直于第一n阱接触，用作保护壁（550） 。

公开(公告)号：US20060231895A1

公开(公告)日：2006-10-19

申请号：US11155062

申请日：2005-06-17

申请人： Charvaka Duvvury ,  Gianluca Boselli ,  John Kunz

发明人： Charvaka Duvvury ,  Gianluca Boselli ,  John Kunz

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0619

摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction 512c. Source 512 has further an ohmic (silicided) connection to contact 513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有与第一n阱的指状接触（513），其接触源极结512c。 源512还具有与触点513的欧姆（硅化）连接。 具有其阴极（521）的指状二极管（520）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到功率（Vdd）并且大致垂直于第一n阱接触，用作保护壁 （550）。

公开(公告)号：US08530301B2

公开(公告)日：2013-09-10

申请号：US12951255

申请日：2010-11-22

申请人： Gianluca Boselli ,  Charvaka Duvvury

发明人： Gianluca Boselli ,  Charvaka Duvvury

IPC分类号： H01L21/8238

CPC分类号： H01L27/0259

摘要： An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region. The terminal of the functional circuit (24, PAD) is coupled to the cathode (36) of the Nwell diode, and the anode (37) of the Nwell diode is connected in series with a path from the drain (44) to the source (43) of the NMOS transistor (200).

摘要翻译： 在包括公共p层（38）的衬底的半导体表面处形成的集成电路（25）包括形成在p层（38）上的功能电路（24），包括多个端子（IN，OUT，I / O）耦合到功能电路（24）。 至少一个ESD保护单元（30;更详细地200）连接到功能电路（24）的多个端子中的至少一个。 保护单元包括至少形成在p层（38）中的第一N阱（37），在第一N阱（37）内的p掺杂扩散层（36），以形成至少一个包含阳极（37）的Nwell二极管， 和阴极（36）。 NMOS晶体管200形成在包含n +源极（43），n +漏极（44）的p层（38）中或上，以及包括源极和漏极之间的p区域（41）的沟道区域，以及栅极 电极（45）在沟道区上的栅极电介质（46）上。 功能电路（24，PAD）的端子耦合到Nwell二极管的阴极（36），Nwell二极管的阳极（37）与从漏极（44）到源极 （200）的（43）。

公开(公告)号：US08176460B2

公开(公告)日：2012-05-08

申请号：US12434578

申请日：2009-05-01

申请人： Gianluca Boselli ,  Jonathan S. Brodsky ,  John E. Kunz, Jr.

发明人： Gianluca Boselli ,  Jonathan S. Brodsky ,  John E. Kunz, Jr.

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5045 ,  H01L27/0248

摘要： An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.

摘要翻译： 公开了ESD保护优化器，一种优化IC的ESD保护和ESD保护优化系统的方法。 在一个实施例中，ESD保护优化器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构进行比较来识别IC的ESD单元和电路，以及（2）ESD电阻确定器 被配置为计算与所述电路串联耦合的电阻值，所述电阻值基于与所识别的ESD单元相关联的保护单元物理属性和与所识别的电路相关联的电路物理属性。

公开(公告)号：US07667243B2

公开(公告)日：2010-02-23

申请号：US11739801

申请日：2007-04-25

申请人： Charvaka Duvvury ,  Gianluca Boselli

发明人： Charvaka Duvvury ,  Gianluca Boselli

IPC分类号： H01L23/62

CPC分类号： H01L27/0255 ,  H01L27/0292

摘要： A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.

摘要翻译： 当I / O焊盘位于电源焊盘（303）和接地电位焊盘（305a）之间时，用于局部保护集成电路输入/输出（I / O）焊盘（301）的ESD事件的半导体器件。 第一二极管311和第二二极管312串联连接，串联的阳极311b与I / O焊盘和阴极312a连接。 第三二极管（304）的阳极（304b）连接到接地焊盘，其阴极（304a）连接到I / O焊盘。 至少一个二极管的串（320）具有连接到与I / O焊盘隔离的第一和第二二极管（节点313）之间的串联的阳极（321b），并且其阳极（323a）连接到接地垫 。 串（320）可以包括三个或更多个二极管。