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12 条记录 (耗时 0.022 秒)

    PMOS electrostatic discharge (ESD) protection device
    1.
    发明授权
    PMOS electrostatic discharge (ESD) protection device 有权
    PMOS静电放电（ESD）保护装置

    公开(公告)号：US07196887B2

    公开(公告)日：2007-03-27

    申请号：US10446369

    申请日：2003-05-28

    申请人： Gianluca Boselli ,  Vijay Kumar Reddy ,  Ekanayake Ajith Amerasekera

    发明人： Gianluca Boselli ,  Vijay Kumar Reddy ,  Ekanayake Ajith Amerasekera

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0266 ,  H01L29/7833

    摘要： A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.

    摘要翻译： 公开了一种PMOS ESD保护器件，其中实施栅极和衬底耦合技术以在正ESD事件期间提供保护。 去除能够根据本发明的一个或多个方面产生的曲线中的快速回转支腿，从而减小了装置导通的触发电压，以便小于对应于第二击穿的第二电压 地区。

    Methods and systems for determining efficacy of stress protection circuitry
    2.
    发明授权
    Methods and systems for determining efficacy of stress protection circuitry 有权
    用于确定应力保护电路功效的方法和系统

    公开(公告)号：US07385383B2

    公开(公告)日：2008-06-10

    申请号：US11145141

    申请日：2005-06-03

    申请人： Vijay Kumar Reddy ,  Gianluca Boselli ,  Jeremy Charles Smith

    发明人： Vijay Kumar Reddy ,  Gianluca Boselli ,  Jeremy Charles Smith

    IPC分类号： G01R19/00 ,  G01R27/28 ,  G06F17/50

    CPC分类号： G01R31/002 ,  H01L27/0251

    摘要： Methods and systems are provided for determining efficacy of stress protection circuitry. The methods and systems employ a ring oscillator that models at least one parameter of a functional circuit to be protected by the stress protection circuit. A stress signal is applied to the ring oscillator and parametric degradation is measured to determine the effectiveness of the stress protection circuit in protecting the ring oscillator. A stress signal can be a voltage or current that stresses the normal operation of a functional circuit. The parametric degradation of the ring oscillator can be correlated to the parametric degradation that would be experienced by the functional circuit.

    摘要翻译： 提供了用于确定应力保护电路的功效的方法和系统。 所述方法和系统采用环形振荡器，其对由应力保护电路保护的功能电路的至少一个参数进行建模。 应力信号被施加到环形振荡器，并且测量参数劣化以确定应力保护电路在保护环形振荡器中的有效性。 应力信号可以是强调功能电路的正常操作的电压或电流。 环形振荡器的参数衰减可以与功能电路将经历的参数降级相关。

    Parameter drift prediction
    4.
    发明授权
    Parameter drift prediction 有权
    参数漂移预测

    公开(公告)号：US08239814B2

    公开(公告)日：2012-08-07

    申请号：US12630920

    申请日：2009-12-04

    申请人： Vijay Kumar Reddy

    发明人： Vijay Kumar Reddy

    IPC分类号： G06F11/22

    CPC分类号： G06F17/5036

    摘要： A set of parameter drifts is recorded over a period of time for each of a series of stress tests on a system at various stress levels. Each set of the recorded parameter drifts is plotted as parameter drift versus time. The plots are then time shifted in relation to a reference plot to form a single parameter drift plot. A non-linear equation is fitted to the single parameter drift plot and then used to predict parameter drift over the life of the system.The non-linear equation may be modified by adding a stress acceleration factor to allow prediction of parameter drift over time at different stress levels.

    摘要翻译： 对于各种应力水平的系统的一系列应力测试中的每一个，一段时间内记录一组参数漂移。 记录的参数漂移的每组被绘制为参数漂移与时间的关系。 然后，绘图相对于参考图进行时移，以形成单个参数漂移图。 将非线性方程拟合到单参数漂移图，然后用于预测系统寿命内的参数漂移。 可以通过加上应力加速度因子来修改非线性方程，以允许在不同应力水平下随时间推移参数漂移的预测。

    Method and system for determining transistor degradation mechanisms
    5.
    发明授权
    Method and system for determining transistor degradation mechanisms 有权
    用于确定晶体管劣化机制的方法和系统

    公开(公告)号：US06933731B2

    公开(公告)日：2005-08-23

    申请号：US10687796

    申请日：2003-10-17

    申请人： Vijay Kumar Reddy ,  Robert L. Pitts

    发明人： Vijay Kumar Reddy ,  Robert L. Pitts

    IPC分类号： G01R27/28 ,  G01R31/26 ,  G06F17/50 ,  H01L21/66 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/34

    摘要： According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay elements. Each delay element operates as a delay element through the use of one or more transistors of only a first type and no transistors of the opposite type. The method further includes operating the ring oscillator and measuring the frequency resulting from the ring oscillator over time. The magnitude of an isolated degradation mechanism is determined based on a comparison of the measured frequency and an expected frequency for the ring oscillator absent degradation.

    摘要翻译： 根据一个实施例，用于隔离晶体管中的劣化机制的方法包括提供具有多个延迟元件的环形振荡器。 每个延迟元件通过使用仅一种第一类型的一个或多个晶体管并且不具有相反类型的晶体管而作为延迟元件工作。 该方法还包括操作环形振荡器并测量环形振荡器随时间产生的频率。 基于测量的频率与环形振荡器的预期频率的比较而不退化来确定分离的降解机制的幅度。

    Tunable stress technique for reliability degradation measurement
    7.
    发明授权
    Tunable stress technique for reliability degradation measurement 有权
    可靠性降解测量的可调压力技术

    公开(公告)号：US07952378B2

    公开(公告)日：2011-05-31

    申请号：US12358510

    申请日：2009-01-23

    申请人： Andrew Marshall ,  Vijay Kumar Reddy

    发明人： Andrew Marshall ,  Vijay Kumar Reddy

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2879 ,  G01R31/2856

    摘要： Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output voltage swings. Two output transistors that varying greatly in the size of their respective channel widths are provided for independently evaluating impacts on the output waveform. The gate control for the smaller transistor is separate from the gate control to the larger transistor. The gate and drain stress can thus be adjusted and evaluated independently.

    摘要翻译： 公开了用于检查RF功率放大器电路中的可靠性如何随着输入到输出电压摆幅的变化而变化的装置和方法。 提供两个输出晶体管，它们各自的通道宽度的大小变化很大，用于独立评估对输出波形的影响。 较小晶体管的栅极控制与栅极控制分离到较大的晶体管。 因此可以独立地调节和评估栅极和漏极应力。

    Parameter Drift Prediction
    8.
    发明申请
    Parameter Drift Prediction 有权
    参数漂移预测

    公开(公告)号：US20100242001A1

    公开(公告)日：2010-09-23

    申请号：US12630920

    申请日：2009-12-04

    申请人： Vijay Kumar Reddy

    发明人： Vijay Kumar Reddy

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A set of parameter drifts is recorded over a period of time for each of a series of stress tests on a system at various stress levels. Each set of the recorded parameter drifts is plotted as parameter drift versus time. The plots are then time shifted in relation to a reference plot to form a single parameter drift plot. A non-linear equation is fitted to the single parameter drift plot and then used to predict parameter drift over the life of the system.The non-linear equation may be modified by adding a stress acceleration factor to allow prediction of parameter drift over time at different stress levels.

    摘要翻译： 对于各种应力水平的系统的一系列应力测试中的每一个，一段时间内记录一组参数漂移。 记录的参数漂移的每组被绘制为参数漂移与时间的关系。 然后，绘图相对于参考图进行时移，以形成单个参数漂移图。 将非线性方程拟合到单参数漂移图，然后用于预测系统寿命内的参数漂移。 可以通过加上应力加速度因子来修改非线性方程，以允许在不同应力水平下随时间推移参数漂移的预测。

    METHODOLOGY FOR ASSESSING DEGRADATION DUE TO RADIO FREQUENCY EXCITATION OF TRANSISTORS
    9.
    发明申请
    METHODOLOGY FOR ASSESSING DEGRADATION DUE TO RADIO FREQUENCY EXCITATION OF TRANSISTORS 有权
    评估无线电频率振荡器降解的方法

    公开(公告)号：US20090167429A1

    公开(公告)日：2009-07-02

    申请号：US12013221

    申请日：2008-01-11

    申请人： Vijay Kumar Reddy ,  Andrew Marshall ,  Siraj Akhtar ,  Srikanth Krishnan ,  Karan Singh Bhatia

    发明人： Vijay Kumar Reddy ,  Andrew Marshall ,  Siraj Akhtar ,  Srikanth Krishnan ,  Karan Singh Bhatia

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2879 ,  G01R31/3161

    摘要： One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.

    摘要翻译： 一个实施例涉及片上功率放大器（PA）测试电路。 在一个实施例中，PA测试电路包括被配置为产生射频（RF）信号的可控振荡器（CO），调谐到射频的并联谐振电路，耦合到CO的预功率放大器（PPA）和 并联谐振电路，PPA被配置为放大并将RF信号从PPA的输出驱动到负载中。 测试电路还可以包括被配置为将来自CO的RF信号耦合到PPA的输入的第一传输门。 PA测试电路的一种测试方法包括用RF信号强迫PPA，测量PPA的特性，从特征测量确定应力退化，并重复应力和特征测量，直到达到最大应力退化或最大应力 已被应用。

    Versatile system for accelerated stress characterization of semiconductor device structures
    10.
    发明授权
    Versatile system for accelerated stress characterization of semiconductor device structures 有权
    用于半导体器件结构加速应力表征的多功能系统

    公开(公告)号：US07026838B2

    公开(公告)日：2006-04-11

    申请号：US10871932

    申请日：2004-06-18

    申请人： Vijay Kumar Reddy ,  Prasun Raha

    发明人： Vijay Kumar Reddy ,  Prasun Raha

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2884 ,  G01R31/275 ,  G01R31/2856

    摘要： The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the given transistor, are disposed in series with one another (202). A plurality of signal taps is operatively associated with each gap between adjacent inverter circuits. Selective circuitry is operatively coupled to the plurality of signal taps, and adapted to output (206) data from a first and a second of the plurality of signal taps. A controlled voltage component (212) is operatively coupled the plurality of inverter circuits, and adapted to supply a desired supply voltage. A controlled signal component (210) is operatively coupled the plurality of inverter circuits, and adapted to supply a signal of a desired frequency thereto. An evaluation component (208) receives signal data from the first and second signal taps for evaluation or processing.

    摘要翻译： 本发明提供一种用于执行给定晶体管（204）的加速应力表征的系统（200）。 由给定晶体管形成的逆变器电路彼此串联设置（202）。 多个信号抽头可操作地与相邻逆变器电路之间的每个间隙相关联。 选择性电路可操作地耦合到多个信号抽头，并且适于从多个信号抽头中的第一和第二信号抽头输出（206）数据。 受控电压分量（212）可操作地耦合多个逆变器电路，并且适于提供期望的电源电压。 受控信号分量（210）可操作地耦合多个逆变器电路，并且适于向其提供期望频率的信号。 评估组件（208）从第一和第二信号抽头接收用于评估或处理的信号数据。