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1.发明申请ADVANCED BACKGROUND ESTIMATION TECHNIQUE AND CIRCUIT FOR A HYPER-SPECTRAL TARGET DETECTION METHOD 有权用于超频谱目标检测方法的高级背景估计技术和电路公开(公告)号：US20110200225A1
公开(公告)日：2011-08-18
申请号：US12707672
申请日：2010-02-17
申请人： Vikas Kukshya , Jose M. Cruz-Albrecht , Roy Matic , Peter Petre , Mark W. Wolboldt , David R. Gerwe
发明人： Vikas Kukshya , Jose M. Cruz-Albrecht , Roy Matic , Peter Petre , Mark W. Wolboldt , David R. Gerwe
IPC分类号： G06K9/00
CPC分类号： G06K9/00496 , G06K9/0063
摘要： A system, circuit and methods for target detection from hyper-spectral image data are disclosed. Filter coefficients are determined using a modified constrained energy minimization (CEM) method. The modified CEM method can operate on a circuit operable to perform constrained linear programming optimization. A filter comprising the filter coefficients is applied to a plurality of pixels of the hyper-spectral image data to form CEM values for the pixels, and one or more target pixels are identified from the CEM values. The process may be repeated to enhance target recognition by using filter coefficients determined by excluding the identified target pixels from the hyper-spectral image data.
摘要翻译： 公开了一种用于从超光谱图像数据进行目标检测的系统，电路和方法。 使用修改的约束能量最小化（CEM）方法确定滤波器系数。 修改的CEM方法可以在可操作以执行约束线性规划优化的电路上操作。 将包括滤波器系数的滤波器应用于超光谱图像数据的多个像素以形成像素的CEM值，并且根据CEM值识别一个或多个目标像素。 可以重复该过程以通过使用通过从超光谱图像数据排除所识别的目标像素而确定的滤波器系数来增强目标识别。
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2.发明授权Advanced background estimation technique and circuit for a hyper-spectral target detection method 有权高分辨率目标检测方法的高级背景估计技术和电路公开(公告)号：US08280111B2
公开(公告)日：2012-10-02
申请号：US12707672
申请日：2010-02-17
申请人： Vikas Kukshya , Jose M. Cruz-Albrecht , Roy Matic , Peter Petre , Mark W. Wolboldt , David R. Gerwe
发明人： Vikas Kukshya , Jose M. Cruz-Albrecht , Roy Matic , Peter Petre , Mark W. Wolboldt , David R. Gerwe
CPC分类号： G06K9/00496 , G06K9/0063
摘要： A system, circuit and methods for target detection from hyper-spectral image data are disclosed. Filter coefficients are determined using a modified constrained energy minimization (CEM) method. The modified CEM method can operate on a circuit operable to perform constrained linear programming optimization. A filter comprising the filter coefficients is applied to a plurality of pixels of the hyper-spectral image data to form CEM values for the pixels, and one or more target pixels are identified from the CEM values. The process may be repeated to enhance target recognition by using filter coefficients determined by excluding the identified target pixels from the hyper-spectral image data.
摘要翻译： 公开了一种用于从超光谱图像数据进行目标检测的系统，电路和方法。 使用修改的约束能量最小化（CEM）方法确定滤波器系数。 修改的CEM方法可以在可操作以执行约束线性规划优化的电路上操作。 将包括滤波器系数的滤波器应用于超光谱图像数据的多个像素以形成像素的CEM值，并且根据CEM值识别一个或多个目标像素。 可以重复该过程以通过使用通过从超光谱图像数据排除所识别的目标像素而确定的滤波器系数来增强目标识别。
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公开(公告)号：US09697462B1
公开(公告)日：2017-07-04
申请号：US14588929
申请日：2015-01-03
CPC分类号： G06N3/04
摘要： A synaptic time-multiplexed (STM) neuromorphic network includes a neural fabric that includes nodes and switches to define inter-nodal connections between selected nodes of the neural fabric. The STM neuromorphic network further includes a neuromorphic controller to form subsets of a set of the inter-nodal connections representing a fully connected neural network. Each subset is formed during a different time slot of a plurality of time slots of a time multiplexing cycle of the STM neuromorphic network. In combination, the inter-nodal connection subsets implement the fully connected neural network. A method of synaptic time multiplexing a neuromorphic network includes providing the neural fabric and forming the subsets of the set of inter-nodal connections.
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4.发明授权Synaptic time multiplexing neuromorphic network that forms subsets of connections during different time slots 有权突触时间复用神经元网络，在不同的时隙内形成连接子集公开(公告)号：US08977578B1
公开(公告)日：2015-03-10
申请号：US13535114
申请日：2012-06-27
CPC分类号： G06N3/04
摘要： A synaptic time-multiplexed (STM) neuromorphic network includes a neural fabric that includes nodes and switches to define inter-nodal connections between selected nodes of the neural fabric. The STM neuromorphic network further includes a neuromorphic controller to form subsets of a set of the inter-nodal connections representing a fully connected neural network. Each subset is formed during a different time slot of a plurality of time slots of a time multiplexing cycle of the STM neuromorphic network. In combination, the inter-nodal connection subsets implement the fully connected neural network. A method of synaptic time multiplexing a neuromorphic network includes providing the neural fabric and forming the subsets of the set of inter-nodal connections.
摘要翻译： 突触时间复用（STM）神经元网络包括神经织构，其包括用于定义神经织物的选定节点之间的节间连接的节点和开关。 STM神经元网络还包括神经形态控制器，以形成代表完全连接的神经网络的一组节点间连接的子集。 每个子集在STM神经形态网络的时间复用周期的多个时隙的不同时隙中形成。 结合在一起，节点间连接子集实现完全连接的神经网络。 突触时间复用神经元网络的方法包括提供神经织物并形成一组节间连接的子集。
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公开(公告)号：US07403144B1
公开(公告)日：2008-07-22
申请号：US11645936
申请日：2006-12-26
申请人： Jose M. Cruz-Albrecht , Peter Petre
发明人： Jose M. Cruz-Albrecht , Peter Petre
IPC分类号： H03M3/00
摘要： A pulse circuit to solve a system of differential equations in the pulse domain based on analog or inputs or time-encoded pulse inputs. Intrinsically linear 1-bit digital to analog converters are used as feedback elements within circuits implementing solutions to a differential equation or to a system of differential equations. The circuits may be used to implement filters. While the input to the circuit may be an analog signal, the internal signals of the circuit are time-encoded current or voltage pulses. Output of the circuit is a time-encoded pulse or a series of time-encoded pulses from which an analog output may be recovered by time decoding.
摘要翻译： 脉冲电路，用于解决基于模拟或输入或时间编码脉冲输入的脉冲域中的微分方程系统。 本质上线性的1位数模转换器用作电路中的反馈元件，实现微分方程或微分方程组的解。 电路可用于实现滤波器。 当电路的输入可以是模拟信号时，电路的内部信号是时间编码的电流或电压脉冲。 电路的输出是时间编码脉冲或一系列时间编码脉冲，通过时间解码可以从中恢复模拟输出。
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公开(公告)号：US06515501B2
公开(公告)日：2003-02-04
申请号：US09873093
申请日：2001-06-01
IPC分类号： H03K19003
CPC分类号： H05K1/025 , H05K1/181 , H05K3/222 , H05K2201/09236 , H05K2201/10212 , H05K2201/10689
摘要： An improved signal buffer configuration has been developed for transmitting communication signals across line traces between ICs on a printed circuit board, printed wiring board, multi-chip module, integrated circuit carrier or package, or other interconnect substrate. For example, in some realizations, multiple ICs having mismatched input and output impedances are mounted on an printed circuit board and communicate with each other via line traces. A signal buffer IC is placed in-line with the connecting line trace. The buffer is sized to fit within the pitch spacing of the line trace and contains an input impedance control circuit and an output impedance control circuit. These impedance control circuits are adapted to receive a control signal to set the input and output impedances of the buffer to correspond to the impedances of the connecting line traces. In this manner, the impedances between the ICs connected by this line trace are effectively matched and transmission line errors between them are reduced.
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公开(公告)号：US08180057B1
公开(公告)日：2012-05-15
申请号：US12793618
申请日：2010-06-03
IPC分类号： H04L9/00
CPC分类号： H03B29/00
摘要： A circuit for generating chaotic signals implemented using heterojunction bipolar transistors (HBTs) and utilized in low probability intercept communications. The HBT chaotic circuit generates truly random analog signals in the GHz range that are non-repeating and deterministic and may not be replicated by preloading a predetermined sequence. A fully differential autonomous chaotic circuit outputs two pairs of chaotic signals to be used in a communication system. As it is impossible to generate identical chaotic signals at the transmitter and receiver sites, the receiver itself sends the chaotic signal to be used for encoding to the transmitter. The receiver includes a chaotic signal generator and digitizes, upconverts, and transmits the generated chaotic signal to the transmitter. The transmitter uses the received chaotic signal to code data to be transmitted. The receiver decodes the transmitted data that is encoded by the chaotic signal to retrieve the transmitted data.
摘要翻译： 用于产生使用异质结双极晶体管（HBT）实现并用于低概率截取通信的混沌信号的电路。 HBT混沌电路在GHz范围内产生非重复和确定性的真实随机模拟信号，并且可能不会通过预加载预定序列来复制。 全差分自主混沌电路输出要在通信系统中使用的两对混沌信号。 由于在发射机和接收站点不可能产生相同的混沌信号，所以接收机本身将发送混沌信号用于编码。 接收机包括混沌信号发生器，数字化，上变频，并将发生的混沌信号发送到发射机。 发射机使用接收到的混沌信号来编码要传输的数据。 接收机对由混沌信号编码的发送数据进行解码以检索发送的数据。
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公开(公告)号：US07795983B1
公开(公告)日：2010-09-14
申请号：US11646176
申请日：2006-12-26
IPC分类号： H03B29/00
CPC分类号： H03B29/00
摘要： A circuit for generating chaotic signals implemented using heterojunction bipolar transistors (HBTs) and utilized in low probability intercept communications. The HBT chaotic circuit generates truly random analog signals in the GHz range that are non-repeating and deterministic and may not be replicated by preloading a predetermined sequence. A fully differential autonomous chaotic circuit outputs two pairs of chaotic signals to be used in a communication system. As it is impossible to generate identical chaotic signals at the transmitter and receiver sites, the receiver itself sends the chaotic signal to be used for encoding to the transmitter. The receiver includes a chaotic signal generator and digitizes, upconverts, and transmits the generated chaotic signal to the transmitter. The transmitter uses the received chaotic signal to code data to be transmitted. The receiver decodes the transmitted data that is encoded by the chaotic signal to retrieve the transmitted data.
摘要翻译： 用于产生使用异质结双极晶体管（HBT）实现并用于低概率截取通信的混沌信号的电路。 HBT混沌电路在GHz范围内产生非重复和确定性的真实随机模拟信号，并且可能不会通过预加载预定序列来复制。 全差分自主混沌电路输出要在通信系统中使用的两对混沌信号。 由于在发射机和接收站点不可能产生相同的混沌信号，所以接收机本身将发送混沌信号用于编码。 接收机包括混沌信号发生器，数字化，上变频，并将发生的混沌信号发送到发射机。 发射机使用接收到的混沌信号来编码要传输的数据。 接收机对由混沌信号编码的发送数据进行解码以检索发送的数据。
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公开(公告)号：US06937175B1
公开(公告)日：2005-08-30
申请号：US10830736
申请日：2004-04-21
CPC分类号： H03F1/3247 , H03F2200/331
摘要： In one embodiment of the present invention, an amplifier circuit is provided which includes a predistorter coupled to a power amplifier. An error detector is coupled to the signal input of the predistorter via a delay circuit and to the power amplifier output. The error detector output is coupled to a delta-sigma modulator and the output of the delta-sigma is coupled to the control input of the predistorter. The predistorter may be constructed to provide an output selected from a set of output characteristic curves, in response to a control signal at the control input. The control input of the predistorter may be a multi-bit discrete input, which may be a binary input, such as for example, a three bit binary input.
摘要翻译： 在本发明的一个实施例中，提供一种放大器电路，其包括耦合到功率放大器的预失真器。 误差检测器通过延迟电路和功率放大器输出耦合到预失真器的信号输入端。 误差检测器输出耦合到Δ-Σ调制器，并且Δ-Σ的输出耦合到预失真器的控制输入端。 预失真器可以被构造成响应于控制输入处的控制信号而提供从一组输出特性曲线中选出的输出。 预失真器的控制输入可以是多位离散输入，其可以是二进制输入，例如三位二进制输入。
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10.发明授权Method and apparatus for using a non-periodic signal to perform clock dithering 有权使用非周期性信号执行时钟抖动的方法和装置公开(公告)号：US06404260B1
公开(公告)日：2002-06-11
申请号：US09783800
申请日：2001-02-13
IPC分类号： G06F104
摘要： One embodiment of the present invention provides a system that uses a non-periodic signal to modulate the period of a clock signal. The system includes a latch with a latch input, a latch output and a clock input. Asserting the clock input of the latch causes a data value at the latch input to be stored into the latch, and to thereby appear at the latch output. The system also includes an inverting delay circuit that receives the clock signal from the latch output and generates an inverted and delayed clock signal, which feeds back into the input of the latch. The clock input of the latch is coupled to the non-periodic signal, so that the non-periodic signal is used to latch the inverted and delayed clock signal, so that the clock signal changes at a non-periodic interval. In one embodiment of the present invention, the inverting delay circuit includes a chain of an odd number of inverters. One embodiment of the present invention additionally includes a chaotic circuit containing three or more energy storage elements for generating the non-periodic signal.
摘要翻译： 本发明的一个实施例提供一种使用非周期信号来调制时钟信号的周期的系统。 该系统包括具有锁存器输入，锁存器输出和时钟输入的锁存器。 断开锁存器的时钟输入使得锁存器输入处的数据值被存储到锁存器中，从而出现在锁存器输出端。 该系统还包括反相延迟电路，其从锁存器输出端接收时钟信号，并产生反相和延迟的时钟信号，其反馈到锁存器的输入端。 锁存器的时钟输入耦合到非周期信号，使得非周期性信号用于锁存反相和延迟的时钟信号，使得时钟信号以非周期性间隔改变。 在本发明的一个实施例中，反相延迟电路包括奇数个反相器的链。 本发明的另一个实施例还包括一个包含三个或更多个用于产生非周期信号的能量存储元件的混沌电路。
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