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1.发明授权Adaptive, intelligent transform-based analog to information converter method and system 失效自适应，基于智能变换的模拟信息转换方法和系统公开(公告)号：US07324036B2
公开(公告)日：2008-01-29
申请号：US10845487
申请日：2004-05-12
申请人： Peter Petre , Shubha Kadambo , Joseph F. Jensen
发明人： Peter Petre , Shubha Kadambo , Joseph F. Jensen
IPC分类号： H03M1/00
CPC分类号： H03M1/121
摘要： The present invention provides an adaptive, intelligent transform based Analog to Information Converter (AIC) for wideband signals by directly converting an analog signal to information (e.g., features, decisions). This direct conversion is achieved by (i) capturing most of the information of a wideband signal via hardware/software implemented mathematical transformations, (ii) effectively removing unwanted signals such as jammer and interfere from the input signal, and (iii) using novel algorithms for highly accurate decision making and feature extraction (e.g., high probability of detection with low probability of false alarm). The jump in the improvement over today's state-of-the-art is in terms of effective and optimum signal information extraction at high-speed.
摘要翻译： 本发明通过将模拟信号直接转换为信息（例如，特征，决策）为宽带信号提供了一种用于宽带信号的自适应智能变换的模拟信息转换器（AIC）。 这种直接转换是通过（i）通过硬件/软件实现的数学变换来捕获宽带信号的大部分信息来实现的，（ii）有效地去除不需要的信号，例如干扰信号和干扰来自输入信号，以及（iii）使用新颖的算法 用于高精度决策和特征提取（例如，具有较低误报概率的高概率检测）。 与当今最先进的技术相比，改进的跳跃是在高速的有效和最佳的信号信息提取方面。
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2.发明授权Highly linear mixer and method for cancelling FET channel resistance modulation 有权高线性混频器和消除FET沟道电阻调制的方法公开(公告)号：US08050644B1
公开(公告)日：2011-11-01
申请号：US12337379
申请日：2008-12-17
申请人： Albert E. Cosand , Joseph F. Jensen
发明人： Albert E. Cosand , Joseph F. Jensen
IPC分类号： H04B1/10
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0023 , H03D2200/0043 , H03D2200/0088 , H04B15/06
摘要： A highly linear mixer and method for cancelling field effect transistor channel resistance modulation are provided. At least a portion of the voltage of an input signal is added to a drive signal to cancel distortion arising from modulation of the voltage of the input signal.
摘要翻译： 提供一种用于消除场效应晶体管沟道电阻调制的高线性混频器和方法。 将输入信号的电压的至少一部分加到驱动信号上，以消除由调制输入信号的电压引起的失真。
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公开(公告)号：US07515084B1
公开(公告)日：2009-04-07
申请号：US11726484
申请日：2007-03-22
IPC分类号： H03M1/60
摘要： A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.
摘要翻译： 数模转换器包括将模拟输入信号转换为异步脉冲序列的时间编码器，将异步脉冲序列转换成并行的脉冲序列流以相对较低速度的脉冲异步DeMUX电路， 数字转换器，异步数字到同步数字转换器，用于产生绝对时间基准的定时参考电路和数字信号处理器。 该架构提供了基于脉冲编码的模数转换，并具有脉冲编码信号的并行数字化方案。
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公开(公告)号：US5812020A
公开(公告)日：1998-09-22
申请号：US862501
申请日：1997-05-23
CPC分类号： H03H11/0472 , H03H11/0444
摘要： A positive current source (PCS) for supplying common mode current. The PCS includes a pair of unity gain inverting single ended amplifiers that are connected in antiparallel across a pair of matched resistors. Alternately, the resistors can be connected across the inverting and non-inverting sides of a differential amplifier. A constant voltage is applied across the resistors to supply the common mode current (I.sub.cm) while maintaining a common mode resistance of R/2 and a differential mode resistance approaching infinity. The PCS has a common mode resistance which is small enough to maintain a stable common mode operating point with process variations providing minimal impact.
摘要翻译： 用于提供共模电流的正电流源（PCS）。 PCS包括一对在一对匹配电阻器上反并联连接的单位增益反相单端放大器。 或者，电阻器可以跨差分放大器的反相和非反相侧连接。 在电阻器之间施加恒定电压以提供共模电流（Icm），同时保持R / 2的共模电阻和差模电阻接近无穷大。 PCS具有共模电阻，其足够小以保持稳定的共模工作点，其中过程变化提供最小的影响。
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公开(公告)号：US07750835B1
公开(公告)日：2010-07-06
申请号：US12266299
申请日：2008-11-06
IPC分类号： H03M1/50
摘要： A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.
摘要翻译： 数模转换器包括将模拟输入信号转换为异步脉冲序列的时间编码器，将异步脉冲序列转换成并行的脉冲序列流以相对较低速度的脉冲异步DeMUX电路， 数字转换器，异步数字到同步数字转换器，用于产生绝对时间基准的定时参考电路和数字信号处理器。 该架构提供了基于脉冲编码的模数转换，并具有脉冲编码信号的并行数字化方案。
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公开(公告)号：US06466147B1
公开(公告)日：2002-10-15
申请号：US09427195
申请日：1999-10-25
申请人： Henrik T. Jensen , Joseph F. Jensen
发明人： Henrik T. Jensen , Joseph F. Jensen
IPC分类号： H03M166
CPC分类号： H03M1/0673 , H03M1/74
摘要： A method and apparatus for digital-to-analog conversion utilizing randomized dynamic element matching for the attenuation of harmonic distortion during the conversion process due to non-ideal circuit behavior is presented. The present invention introduces a new DEM approach that results in a simplified DAC architecture relative to previous DACs, while preserving optimal spurious-free dynamic range (SFDR). The particular topology utilized involves the use of a bank of DAC-elements, preferably 1-bit DAC elements, the outputs of which are summed to yield a single multiple-level DAC. During each conversion cycle, random selection is used to determine the addresses of the DAC-elements used in order to “scramble” the DAC noise arising from each individual 1-bit DAC.
摘要翻译： 提出了一种使用随机动态元件匹配的数模转换方法和装置，用于由于非理想电路特性而导致的转换过程中的谐波失真衰减。 本发明引入了一种新的DEM方法，其相对于先前的DAC产生简化的DAC架构，同时保持了最佳的无杂散动态范围（SFDR）。 所使用的特定拓扑包括使用一组DAC元件，优选地是1位DAC元件，其输出相加以产生单个多电平DAC。 在每个转换周期期间，随机选择用于确定所使用的DAC元件的地址，以便“扰乱”每个单独1位DAC产生的DAC噪声。
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公开(公告)号：US4872010A
公开(公告)日：1989-10-03
申请号：US153750
申请日：1988-02-08
IPC分类号： H01L21/265 , H01L27/12 , H01L29/06 , H01L29/78 , H01L29/786 , H03M1/00 , H03M1/36
CPC分类号： H01L29/78696 , H01L27/12 , H01L29/0692 , H01L29/7838 , H01L29/78612 , H01L29/78657 , H03M1/361
摘要： An analog-to-digital converter 10 employs a series of comparators 12, 14, 16 and 18. Each comparator includes at least one inverter consisting of a CMOS transistor pair including a P-channel transistor 22 and N-channel transistor 24. The threshold levels of the transistors 22, 24 are modified using focused ion beam implantation techniques to provide the comparators with monotonically increasing transistion levels.
摘要翻译： 模拟 - 数字转换器10采用一系列比较器12,14,16和18.每个比较器包括至少一个由包括P沟道晶体管22和N沟道晶体管24的CMOS晶体管对组成的反相器。阈值 使用聚焦离子束注入技术来修改晶体管22,24的电平，以使比较器具有单调递增的电流电平。
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公开(公告)号：US07948869B2
公开(公告)日：2011-05-24
申请号：US11946844
申请日：2007-11-29
IPC分类号： H04J7/00
CPC分类号： H04B14/026
摘要： The present invention relates to a digital communication architecture based upon the concept of time encoding. In one aspect, systems provide time-encoding-based digital communication, the systems comprising a transmitter, a communication channel, and a receiver. In another aspect, methods for digital communication comprise time encoding digital input data and then transmitting the resultant asynchronous pulse signal to a receiver that converts the asynchronous pulse signal back into digital symbols. Methods of providing a digital communication link can include (i) providing digital symbols, (ii) time encoding the digital symbols to generate asynchronous pulse signals, (iii) communicating switching times of the signals to a receiver, and (iv) digitizing in parallel and reconstructing the digital symbols. The methods and systems of the invention can utilize existing chip-scale circuit technologies and can be characterized by link capacities of 50 Gbit/sec, 100 Gbit/sec, 200 Gbit/sec, or higher.
摘要翻译： 本发明涉及一种基于时间编码概念的数字通信体系结构。 在一个方面，系统提供基于时间编码的数字通信，所述系统包括发射机，通信信道和接收机。 在另一方面，用于数字通信的方法包括对数字输入数据进行时间编码，然后将合成的异步脉冲信号发送到将异步脉冲信号转换回数字符号的接收机。 提供数字通信链路的方法可以包括（i）提供数字符号，（ii）对数字符号进行时间编码以产生异步脉冲信号，（iii）将信号的切换时间传送到接收机，以及（iv）并行数字化 并重建数字符号。 本发明的方法和系统可以利用现有的芯片级电路技术，其特点可以是50Gbit / s，100Gbit / sec，200Gbit / sec或更高的链路容量。
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公开(公告)号：US07016421B2
公开(公告)日：2006-03-21
申请号：US10280416
申请日：2002-10-25
申请人： Daniel Yap , Joseph F. Jensen
发明人： Daniel Yap , Joseph F. Jensen
IPC分类号： H04B14/06
摘要： A Delta-Sigma Analog-to-Digital Converter (ADC) that can have a very high sampling rate (over 100 GHz) and which is preferably optically sampled to help achieve its very high sampling rate. The sampling rate can be many times higher than the regeneration speed of the electronic quantizers used in the ADC.
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公开(公告)号：US08180057B1
公开(公告)日：2012-05-15
申请号：US12793618
申请日：2010-06-03
IPC分类号： H04L9/00
CPC分类号： H03B29/00
摘要： A circuit for generating chaotic signals implemented using heterojunction bipolar transistors (HBTs) and utilized in low probability intercept communications. The HBT chaotic circuit generates truly random analog signals in the GHz range that are non-repeating and deterministic and may not be replicated by preloading a predetermined sequence. A fully differential autonomous chaotic circuit outputs two pairs of chaotic signals to be used in a communication system. As it is impossible to generate identical chaotic signals at the transmitter and receiver sites, the receiver itself sends the chaotic signal to be used for encoding to the transmitter. The receiver includes a chaotic signal generator and digitizes, upconverts, and transmits the generated chaotic signal to the transmitter. The transmitter uses the received chaotic signal to code data to be transmitted. The receiver decodes the transmitted data that is encoded by the chaotic signal to retrieve the transmitted data.
摘要翻译： 用于产生使用异质结双极晶体管（HBT）实现并用于低概率截取通信的混沌信号的电路。 HBT混沌电路在GHz范围内产生非重复和确定性的真实随机模拟信号，并且可能不会通过预加载预定序列来复制。 全差分自主混沌电路输出要在通信系统中使用的两对混沌信号。 由于在发射机和接收站点不可能产生相同的混沌信号，所以接收机本身将发送混沌信号用于编码。 接收机包括混沌信号发生器，数字化，上变频，并将发生的混沌信号发送到发射机。 发射机使用接收到的混沌信号来编码要传输的数据。 接收机对由混沌信号编码的发送数据进行解码以检索发送的数据。
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