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公开(公告)号：US08180057B1
公开(公告)日：2012-05-15
申请号：US12793618
申请日：2010-06-03
IPC分类号： H04L9/00
CPC分类号： H03B29/00
摘要： A circuit for generating chaotic signals implemented using heterojunction bipolar transistors (HBTs) and utilized in low probability intercept communications. The HBT chaotic circuit generates truly random analog signals in the GHz range that are non-repeating and deterministic and may not be replicated by preloading a predetermined sequence. A fully differential autonomous chaotic circuit outputs two pairs of chaotic signals to be used in a communication system. As it is impossible to generate identical chaotic signals at the transmitter and receiver sites, the receiver itself sends the chaotic signal to be used for encoding to the transmitter. The receiver includes a chaotic signal generator and digitizes, upconverts, and transmits the generated chaotic signal to the transmitter. The transmitter uses the received chaotic signal to code data to be transmitted. The receiver decodes the transmitted data that is encoded by the chaotic signal to retrieve the transmitted data.
摘要翻译： 用于产生使用异质结双极晶体管（HBT）实现并用于低概率截取通信的混沌信号的电路。 HBT混沌电路在GHz范围内产生非重复和确定性的真实随机模拟信号，并且可能不会通过预加载预定序列来复制。 全差分自主混沌电路输出要在通信系统中使用的两对混沌信号。 由于在发射机和接收站点不可能产生相同的混沌信号，所以接收机本身将发送混沌信号用于编码。 接收机包括混沌信号发生器，数字化，上变频，并将发生的混沌信号发送到发射机。 发射机使用接收到的混沌信号来编码要传输的数据。 接收机对由混沌信号编码的发送数据进行解码以检索发送的数据。
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公开(公告)号：US07795983B1
公开(公告)日：2010-09-14
申请号：US11646176
申请日：2006-12-26
IPC分类号： H03B29/00
CPC分类号： H03B29/00
摘要： A circuit for generating chaotic signals implemented using heterojunction bipolar transistors (HBTs) and utilized in low probability intercept communications. The HBT chaotic circuit generates truly random analog signals in the GHz range that are non-repeating and deterministic and may not be replicated by preloading a predetermined sequence. A fully differential autonomous chaotic circuit outputs two pairs of chaotic signals to be used in a communication system. As it is impossible to generate identical chaotic signals at the transmitter and receiver sites, the receiver itself sends the chaotic signal to be used for encoding to the transmitter. The receiver includes a chaotic signal generator and digitizes, upconverts, and transmits the generated chaotic signal to the transmitter. The transmitter uses the received chaotic signal to code data to be transmitted. The receiver decodes the transmitted data that is encoded by the chaotic signal to retrieve the transmitted data.
摘要翻译： 用于产生使用异质结双极晶体管（HBT）实现并用于低概率截取通信的混沌信号的电路。 HBT混沌电路在GHz范围内产生非重复和确定性的真实随机模拟信号，并且可能不会通过预加载预定序列来复制。 全差分自主混沌电路输出要在通信系统中使用的两对混沌信号。 由于在发射机和接收站点不可能产生相同的混沌信号，所以接收机本身将发送混沌信号用于编码。 接收机包括混沌信号发生器，数字化，上变频，并将发生的混沌信号发送到发射机。 发射机使用接收到的混沌信号来编码要传输的数据。 接收机对由混沌信号编码的发送数据进行解码以检索发送的数据。
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3.发明授权Integrated structure with transistors and schottky diodes and process for fabricating the same 有权具有晶体管和肖特基二极管的集成结构及其制造方法公开(公告)号：US08368119B1
公开(公告)日：2013-02-05
申请号：US13111771
申请日：2011-05-19
申请人： Louis Luh , Keh-Chung Wang , Wah S. Wong , Miroslav Micovic , David Chow , Don Hitko
发明人： Louis Luh , Keh-Chung Wang , Wah S. Wong , Miroslav Micovic , David Chow , Don Hitko
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605 , H01L27/0629 , H01L29/08 , H01L29/872
摘要： A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.
摘要翻译： 公开了一种用于制造包括高电子迁移率晶体管（HEMT）和肖特基二极管的集成III族氮化物结构的方法及其结果。 使得垂直结肖特基二极管的集成成为可能，并且寄生电容和电阻以及二极管的物理尺寸最小化。 还公开了一种制造包括双异质结构场效应晶体管（DHFET）和肖特基二极管的集成III族氮化物结构的方法及其结果。
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公开(公告)号：US20060202720A1
公开(公告)日：2006-09-14
申请号：US11076621
申请日：2005-03-10
申请人： Louis Luh , Keh-Chung Wang
发明人： Louis Luh , Keh-Chung Wang
IPC分类号： H01L29/06
摘要： A comparator uses two resonant tunneling diodes (RTDs) in series with resistors of the latch element of the comparator. By inserting two RTD diodes in series with resistors, the negative resistance of the first and the second RTD diodes reduces the effective RC time constants of the resistors and latch, leading to a faster regeneration during a latching mode of the comparator than achieved with alternative designs.
摘要翻译： 比较器使用与比较器的锁存元件的电阻串联的两个谐振隧道二极管（RTD）。 通过将两个RTD二极管与电阻器串联，第一个和第二个RTD二极管的负电阻降低了电阻和锁存器的有效RC时间常数，从而在比较器的锁存模式下实现更快的再生，而不是用替代设计 。
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5.发明授权公开(公告)号：US07495592B1
公开(公告)日：2009-02-24
申请号：US11261746
申请日：2005-10-27
申请人： Jeong-Sun Moon , Keh-Chung Wang
发明人： Jeong-Sun Moon , Keh-Chung Wang
IPC分类号： H03M1/00
CPC分类号： H03M1/368
摘要： A voltage comparator including a quantum tunneling coupled transistor and a method for tuning the voltage comparator. The comparator includes a quantum tunneling coupled transistor coupled to a resistor and is capable of operating above 10 Giga-samples-per-second or a clock rate of 10 GHz. The comparator has a low power consumption of about 1 mW excluding the power required for clock generation and independent from the sampling rate. The threshold or reference voltage of the comparator is controllable by adjusting the pulse height of the clock signal. The comparator has relatively low hysteresis estimated at about 1 mV.
摘要翻译： 一种包括量子隧道耦合晶体管的电压比较器和用于调谐电压比较器的方法。 比较器包括耦合到电阻器的量子隧道耦合晶体管，并且能够以超过10千兆采样/秒或10GHz的时钟速率工作。 比较器具有约1mW的低功耗，不包括时钟产生所需的功率，并且独立于采样率。 通过调整时钟信号的脉冲高度可以控制比较器的阈值或参考电压。 比较器估计的滞后相对较低，约为1 mV。
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公开(公告)号：US07202708B2
公开(公告)日：2007-04-10
申请号：US11076621
申请日：2005-03-10
申请人： Louis Luh , Keh-Chung Wang
发明人： Louis Luh , Keh-Chung Wang
摘要： A comparator uses two resonant tunneling diodes (RTDs) in series with resistors of the latch element of the comparator. By inserting two RTD diodes in series with resistors, the negative resistance of the first and the second RTD diodes reduces the effective RC time constants of the resistors and latch, leading to a faster regeneration during a latching mode of the comparator than achieved with alternative designs.
摘要翻译： 比较器使用与比较器的锁存元件的电阻串联的两个谐振隧道二极管（RTD）。 通过将两个RTD二极管与电阻器串联，第一个和第二个RTD二极管的负电阻降低了电阻和锁存器的有效RC时间常数，从而在比较器的锁存模式下实现更快的再生，而不是用替代设计 。
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7.发明授权Integrated structure with transistors and Schottky diodes and process for fabricating the same 有权具有晶体管和肖特基二极管的集成结构及其制造方法公开(公告)号：US07989277B1
公开(公告)日：2011-08-02
申请号：US11853694
申请日：2007-09-11
申请人： Louis Luh , Keh-Chung Wang , Wah S. Wong , Miroslav Micovic , David Chow , Don Hitko
发明人： Louis Luh , Keh-Chung Wang , Wah S. Wong , Miroslav Micovic , David Chow , Don Hitko
IPC分类号： H01L21/338
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605 , H01L27/0629 , H01L29/08 , H01L29/872
摘要： A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.
摘要翻译： 公开了一种用于制造包括高电子迁移率晶体管（HEMT）和肖特基二极管的集成III族氮化物结构的方法及其结果。 使得垂直结肖特基二极管的集成成为可能，并且寄生电容和电阻以及二极管的物理尺寸最小化。 还公开了一种制造包括双异质结构场效应晶体管（DHFET）和肖特基二极管的集成III族氮化物结构的方法及其结果。
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公开(公告)号：US07852153B1
公开(公告)日：2010-12-14
申请号：US12257948
申请日：2008-10-24
IPC分类号： H03G5/16
CPC分类号： H03G3/004 , H03F1/0244 , H03F1/0272 , H03F3/19 , H03F2200/207 , H03F2200/321 , H03F2200/411 , H03F2200/451
摘要： A post-distortion method for cascading amplifier stages in a two-stage microwave power amplifier and a dynamic biasing method using back-end processing for correcting nonlinearity in the power amplifier output. A first or driver stage biased in a near-A region with low distortion is cascaded with a second or power stage biased in a near-C region with high efficiency. The amplitude and phase responses of the two stages compensate another to yield a more linear overall gain for the overall power amplifier. The dynamic biasing scheme modulates the source to drain voltages of the transistors used in the amplifier stages based on the harmonics in amplifier output in order to minimize the harmonics and correct non-linearity in the output.
摘要翻译： 用于两级微波功率放大器级联放大器级的后失真方法和使用后端处理来校正功率放大器输出中的非线性的动态偏置方法。 偏置在具有低失真的近A区域中的第一或者驱动级与以C效率高的偏置在近C区域的第二或功率级级联。 两级的振幅和相位响应补偿另一个，以产生整个功率放大器的更线性的总增益。 动态偏置方案基于放大器输出中的谐波将源极放大到放大器级中使用的晶体管的漏极电压，以便最小化谐波和校正输出中的非线性。
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公开(公告)号：US07477102B1
公开(公告)日：2009-01-13
申请号：US11485037
申请日：2006-07-11
IPC分类号： H03G5/16
CPC分类号： H03G3/004 , H03F1/0244 , H03F1/0272 , H03F3/19 , H03F2200/207 , H03F2200/321 , H03F2200/411 , H03F2200/451
摘要： A post-distortion method for cascading amplifier stages in a two-stage microwave power amplifier and a dynamic biasing method using back-end processing for correcting nonlinearity in the power amplifier output. A first or driver stage biased in a near-A region with low distortion is cascaded with a second or power stage biased in a near-C region with high efficiency. The amplitude and phase responses of the two stages compensate another to yield a more linear overall gain for the overall power amplifier. The dynamic biasing scheme modulates the source to drain voltages of the transistors used in the amplifier stages based on the harmonics in amplifier output in order to minimize the harmonics and correct non-linearity in the output.
摘要翻译： 用于两级微波功率放大器级联放大器级的后失真方法和使用后端处理来校正功率放大器输出中的非线性的动态偏置方法。 偏置在具有低失真的近A区域中的第一或者驱动级与以C效率高的偏置在近C区域的第二或功率级级联。 两级的振幅和相位响应补偿另一个，以产生整个功率放大器的更线性的总增益。 动态偏置方案基于放大器输出中的谐波将源极放大到放大器级中使用的晶体管的漏极电压，以便最小化谐波和校正输出中的非线性。
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10.发明授权
公开(公告)号：US4807008A
公开(公告)日：1989-02-21
申请号：US095974
申请日：1987-09-14
IPC分类号： G11C11/411 , H01L27/06 , H01L27/102 , H01L29/737 , H01L29/72
CPC分类号： G11C11/4113 , H01L27/0605 , H01L27/1025 , H01L29/7378
摘要： A heterostructure complementary transistor switch (HCTS) is fabricated using epitaxial layers on a substrate to form the desired P-N-P-N (or N-P-N-P) complementary structure in III-V compound semiconductor materials. Two HCTS are formed on a single substrate to form a memory cell. A collector and a base on one of the HCTs are connected to a base and a collector, respectively, on the other HCTS to form the memory cell.
摘要翻译： 使用外延层在衬底上制造异质结互补晶体管开关（HCTS），以在III-V族化合物半导体材料中形成所需的P-N-P-N（或N-P-N-P）互补结构。 在单个衬底上形成两个HCTS以形成存储单元。 一个HCT上的集电极和基极分别在另一个HCTS上连接到基极和集电极，以形成存储器单元。
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