公开(公告)号：US20070128736A1

公开(公告)日：2007-06-07

申请号：US11328933

申请日：2006-01-10

申请人： Vincent Chang ,  Fong-Yu Yen ,  Peng-Soon Lim ,  Jin Ying ,  Hun-Jan Tao

发明人： Vincent Chang ,  Fong-Yu Yen ,  Peng-Soon Lim ,  Jin Ying ,  Hun-Jan Tao

IPC分类号： H01L21/00

CPC分类号： H01L21/02175 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.

摘要翻译： 提供具有高k电介质的半导体结构及其制造方法。 一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。 一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。 形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。 具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。 所有氧化金属的原子比在非晶高k电介质层内基本均匀。

公开(公告)号：US07824990B2

公开(公告)日：2010-11-02

申请号：US11328933

申请日：2006-01-10

申请人： Vincent S. Chang ,  Fong-Yu Yen ,  Peng-Soon Lim ,  Jin Ying ,  Hun-Jan Tao

发明人： Vincent S. Chang ,  Fong-Yu Yen ,  Peng-Soon Lim ,  Jin Ying ,  Hun-Jan Tao

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/02175 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.

摘要翻译： 提供具有高k电介质的半导体结构及其制造方法。 一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。 一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。 形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。 具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。 所有氧化金属的原子比在非晶高k电介质层内基本均匀。

公开(公告)号：US20080096336A1

公开(公告)日：2008-04-24

申请号：US11583500

申请日：2006-10-18

申请人： Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

发明人： Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

IPC分类号： H01L21/337

CPC分类号： H01L21/823814 ,  H01L21/28097 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7848

摘要： An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.

摘要翻译： n-FET和p-FET各自具有升高的源极/漏极结构。 可选地，p-FET升高的SOURCE / DRAIN结构从形成在衬底中的p-FET凹槽外延生长。 可选地，n-FET升高的SOURCE / DRAIN结构从形成在衬底中的n-FET凹槽外延生长。 即使结构可能具有不同的材料和/或不同的结构高度，n-FET和p-FET升高源极/漏极结构都是硅化的。 对于n-FET和p-FET升高的源极/漏极结构，至少对源极/漏极结构硅化物的热处理部分同时进行。 此外，p-FET栅电极，n-FET栅电极或两者可以可选地与n-FET和p-FET升高源极/漏极结构同时（相同的金属和/或相同的热处理步骤）硅化 ， 分别; 即使栅电极可以具有不同的材料，不同的硅化物金属和/或不同的电极高度。 在n-FET和p-FET升高源极/漏极结构上形成的硅化物优选不超过约250埃延伸到衬底的顶表面下方; 并且可以选择结构高度来提供这一点。

公开(公告)号：US07465634B2

公开(公告)日：2008-12-16

申请号：US11583500

申请日：2006-10-18

申请人： Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

发明人： Peng-Soon Lim ,  Yong-Tian Hou ,  Jin Ying ,  Hun-Jan Tao

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/28097 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7848

摘要： An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.

公开(公告)号：US08441107B2

公开(公告)日：2013-05-14

申请号：US13599507

申请日：2012-08-30

申请人： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

发明人： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

IPC分类号： H01L29/06

CPC分类号： H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

摘要翻译： 一种装置包括第一装置。 第一装置包括第一突起和第一栅极结构，第一突起从衬底向上延伸并且在其中具有第一沟道区域，并且第一栅极结构接合与第一沟道区相邻的第一突起。 第一结构包括在第一通道区域上的开口，以及设置在开口中的具有低电阻率的保形的纯金属。 该装置还包括第二装置，其包括第二突起和第二栅极结构，第二突起从基板向上延伸并且在其中具有第二通道区域，并且第二栅极结构接合与第二通道区域相邻的第二突出部。 第二结构包括设置在第二通道区域上的硅化物，其中硅化物包括设置在开口中的相同金属的金属。

公开(公告)号：US08258587B2

公开(公告)日：2012-09-04

申请号：US12561358

申请日：2009-09-17

申请人： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

发明人： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/7833

摘要： The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.

摘要翻译： 本公开提供了制造具有金属栅极叠层的半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在高k电介质材料层上形成金属栅极层; 在所述金属栅极层上形成顶栅层; 图案化顶栅层，金属栅极层和高k电介质材料层以形成栅叠层; 执行蚀刻工艺以选择性地凹陷金属栅极层; 以及在所述栅极堆叠的侧壁上形成栅极间隔物。

公开(公告)号：US08193081B2

公开(公告)日：2012-06-05

申请号：US12582031

申请日：2009-10-20

申请人： Peng-Soon Lim ,  Meng-Hsuan Chan ,  Kuang-Yuan Hsu

发明人： Peng-Soon Lim ,  Meng-Hsuan Chan ,  Kuang-Yuan Hsu

IPC分类号： H01L21/283

CPC分类号： H01L29/4236 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66621

摘要： A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

摘要翻译： 一种方法包括提供具有栅极沟槽的半导体衬底，并且使用物理气相沉积（PVD）工艺在衬底上沉积金属层以部分地填充沟槽。 金属层包括比底部更薄的底部部分和侧壁部分。 所述方法还包括在所述金属层上形成涂层，使所述涂层回蚀刻，使得所述涂层的一部分保护所述沟槽内的所述金属层的一部分，以及去除所述金属层的未被保护的部分。 不同的方面涉及一种半导体器件，其包括包括具有顶表面的沟槽的栅极和在沟槽上形成的金属层，其中金属层包括侧壁部分和底部，并且其中侧壁部分比 底部。

公开(公告)号：US09048334B2

公开(公告)日：2015-06-02

申请号：US13214996

申请日：2011-08-22

申请人： Peng-Soon Lim ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

发明人： Peng-Soon Lim ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/31105 ,  H01L21/823456 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate structure comprises a metal layer partially filling a trench of the metal gate structure. The metal layer comprises a first metal sidewall, a second metal sidewall and a metal bottom layer. By employing an uneven protection layer during an etching back process, the thickness of the first metal sidewall is less than the thickness of the metal bottom layer and the thickness of the second metal sidewall is less than the thickness of the metal bottom layer. The thin sidewalls allow extra space for subsequent metal-fill processes.

摘要翻译： 金属栅极结构包括部分地填充金属栅极结构的沟槽的金属层。 金属层包括第一金属侧壁，第二金属侧壁和金属底层。 通过在回蚀处理中采用不均匀的保护层，第一金属侧壁的厚度小于金属底层的厚度，第二金属侧壁的厚度小于金属底层的厚度。 薄的侧壁为后续的金属填充过程提供了额外的空间。

公开(公告)号：US20130049109A1

公开(公告)日：2013-02-28

申请号：US13214996

申请日：2011-08-22

申请人： Peng-Soon Lim ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

发明人： Peng-Soon Lim ,  Da-Yuan Lee ,  Kuang-Yuan Hsu

IPC分类号： H01L27/088 ,  H01L21/283 ,  H01L23/48

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/31105 ,  H01L21/823456 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate structure comprises a metal layer partially filling a trench of the metal gate structure. The metal layer comprises a first metal sidewall, a second metal sidewall and a metal bottom layer. By employing an uneven protection layer during an etching back process, the thickness of the first metal sidewall is less than the thickness of the metal bottom layer and the thickness of the second metal sidewall is less than the thickness of the metal bottom layer. The thin sidewalls allow extra space for subsequent metal-fill processes.

摘要翻译： 金属栅极结构包括部分地填充金属栅极结构的沟槽的金属层。 金属层包括第一金属侧壁，第二金属侧壁和金属底层。 通过在回蚀处理中采用不均匀的保护层，第一金属侧壁的厚度小于金属底层的厚度，第二金属侧壁的厚度小于金属底层的厚度。 薄的侧壁为后续的金属填充过程提供了额外的空间。

公开(公告)号：US20120319192A1

公开(公告)日：2012-12-20

申请号：US13599507

申请日：2012-08-30

申请人： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

发明人： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

IPC分类号： H01L27/092 ,  H01L27/088

CPC分类号： H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

摘要翻译： 一种装置包括第一装置。 第一装置包括第一突起和第一栅极结构，第一突起从衬底向上延伸并且在其中具有第一沟道区域，并且第一栅极结构接合与第一沟道区相邻的第一突起。 第一结构包括在第一通道区域上的开口，以及设置在开口中的具有低电阻率的保形的纯金属。 该装置还包括第二装置，其包括第二突起和第二栅极结构，第二突起从基板向上延伸并且在其中具有第二通道区域，并且第二栅极结构接合与第二通道区域相邻的第二突出部。 第二结构包括设置在第二通道区域上的硅化物，其中硅化物包括设置在开口中的相同金属的金属。