公开(公告)号：US08258587B2

公开(公告)日：2012-09-04

申请号：US12561358

申请日：2009-09-17

申请人： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

发明人： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/7833

摘要： The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.

摘要翻译： 本公开提供了制造具有金属栅极叠层的半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在高k电介质材料层上形成金属栅极层; 在所述金属栅极层上形成顶栅层; 图案化顶栅层，金属栅极层和高k电介质材料层以形成栅叠层; 执行蚀刻工艺以选择性地凹陷金属栅极层; 以及在所述栅极堆叠的侧壁上形成栅极间隔物。

公开(公告)号：US08679926B2

公开(公告)日：2014-03-25

申请号：US13232154

申请日：2011-09-14

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US20120003804A1

公开(公告)日：2012-01-05

申请号：US13232154

申请日：2011-09-14

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US08030718B2

公开(公告)日：2011-10-04

申请号：US12424170

申请日：2009-04-15

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US20100065925A1

公开(公告)日：2010-03-18

申请号：US12424170

申请日：2009-04-15

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US07759744B2

公开(公告)日：2010-07-20

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62 ,  H01L27/10 ,  H01L29/73

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，在硅衬底102上包括第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数膜的P型MOSFET 120 12和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。第一 高介电常数膜111和第二高介电常数膜112含有选自Hf和Zr的一种或多种元素。

公开(公告)号：US08324090B2

公开(公告)日：2012-12-04

申请号：US12338787

申请日：2008-12-18

申请人： Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Yong-Tian Hou ,  Carlos H. Diaz

发明人： Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Yong-Tian Hou ,  Carlos H. Diaz

IPC分类号： H01L21/4763 ,  H01L25/11 ,  H01L29/78

CPC分类号： H01L29/4925 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和 第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层 所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。 第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和 金属层。

公开(公告)号：US20060145265A1

公开(公告)日：2006-07-06

申请号：US11300419

申请日：2005-12-15

申请人： Yuri Masuoka ,  Naohiko Kimizuka ,  Kiyotaka Imai ,  Toshiyuki Iwamoto

发明人： Yuri Masuoka ,  Naohiko Kimizuka ,  Kiyotaka Imai ,  Toshiyuki Iwamoto

IPC分类号： H01L29/94

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： While forming an N-type MOSFET 118 and a P-type MOSFET 120 within regions operating using the same power supply voltage, thickness of a gate insulating film 106a of an N-type MOSFET 118 is made to be thicker than thickness of a gate insulating film 106b of a P-type MOSFET 120.

摘要翻译： 在使用相同电源电压工作的区域内形成N型MOSFET 118和P型MOSFET 120时，使N型MOSFET118的栅极绝缘膜106a的厚度比栅极厚度厚 P型MOSFET120的绝缘膜106b。

公开(公告)号：US20050253181A1

公开(公告)日：2005-11-17

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L31/119

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数的P型MOSFET 120 膜112和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。 第一高介电常数膜111和第二高介电常数膜112包含从由Hf和Zr组成的组中选择的一种或多种元素。

公开(公告)号：US07754570B2

公开(公告)日：2010-07-13

申请号：US11210873

申请日：2005-08-25

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto

IPC分类号： H01L21/336

CPC分类号： H01L29/518 ,  H01L21/0214 ,  H01L21/02142 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/28185 ,  H01L21/28238 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/1033

摘要： Threshold voltage of a field effect transistor is successfully adjusted with a smaller dose of an impurity, as compared with a conventional adjustment of the threshold voltage only by doping an impurity into the channel region. A semiconductor device 100 has a silicon substrate 101 and a P-type MOSFET 103 comprising a SiON film 113 formed on the silicon substrate 101, and a polycrystalline silicon film 106. Any one of, or two or more of metals selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ti, Ta and W are allowed to reside at the interface 115 between the polycrystalline silicon film 106 and the SiON film 113, and concentration of the metal(s) at the interface 115 is adjusted to 5×1013 atoms/cm2 or more and less than 1.4×1015 atoms/cm2.

摘要翻译： 与仅通过将杂质掺杂到沟道区域中的阈值电压的常规调节相比，场效应晶体管的阈值电压被成功地用较小剂量的杂质调节。 半导体器件100具有硅衬底101和包括形成在硅衬底101上的SiON膜113的P型MOSFET 103和多晶硅膜106.选自以下的金属中的任何一种或两种以上选自 的Hf，Zr，Al，La，Pr，Y，Ti，Ta和W被放置在多晶硅膜106和SiON膜113之间的界面115处，并且界面115处的金属的浓度 调整为5×1013原子/ cm 2以上且小于1.4×1015原子/ cm 2。