公开(公告)号：US20070138657A1

公开(公告)日：2007-06-21

申请号：US11314272

申请日：2005-12-21

申请人： Vincenzo Condorelli ,  Claudius Feger ,  Kevin Gotze ,  Nihad Hadzic ,  John Knickerbocker ,  Edmund Sprogis

发明人： Vincenzo Condorelli ,  Claudius Feger ,  Kevin Gotze ,  Nihad Hadzic ,  John Knickerbocker ,  Edmund Sprogis

IPC分类号： H01L23/28

CPC分类号： H01L23/576 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19107 ,  Y10T29/53039 ,  Y10T29/53052 ,  Y10T29/53178 ,  H01L2924/00

摘要： A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

摘要翻译： 提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。 衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。 电导体围绕导电路径。 监控电路检测一个或多个电导体的连续性的断裂，并且优选地使组件不可操作。 优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

公开(公告)号：US20070255966A1

公开(公告)日：2007-11-01

申请号：US11416005

申请日：2006-05-01

申请人： Vincenzo Condorelli ,  Kevin Gotze ,  Nihad Hadzic

发明人： Vincenzo Condorelli ,  Kevin Gotze ,  Nihad Hadzic

IPC分类号： G06F12/14

CPC分类号： G06F21/87

摘要： A cryptographic circuit with voltage island-based tamper detection and response is disclosed. The circuit includes a voltage island having at least one monitoring circuit and a first storage area for security parameters. The circuit also includes a second storage area for key storage and management logic to tamper the security parameters upon detection of an environmental failure.

摘要翻译： 公开了一种具有电压岛式篡改检测和响应的加密电路。 电路包括具有至少一个监控电路的电压岛和用于安全参数的第一存储区域。 电路还包括用于密钥存储和管理逻辑的第二存储区域，用于在检测到环境故障时篡改安全参数。

公开(公告)号：US20060086534A1

公开(公告)日：2006-04-27

申请号：US11163609

申请日：2005-10-25

申请人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic ,  Kevin Gotze ,  Tamas Visegrady

发明人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic ,  Kevin Gotze ,  Tamas Visegrady

IPC分类号： H05K1/11 ,  H01R12/04

CPC分类号： H05K3/1258 ,  H05K1/0275 ,  H05K1/095 ,  H05K1/167 ,  H05K3/108 ,  H05K3/28 ,  H05K2201/10151 ,  H05K2203/0568 ,  Y10T29/49155

摘要： A method for embedding tamper proof layers and discrete components into a printed circuit board stack-up is disclosed. According to this method, a plating mask is applied on a base substrate to cover partially one of its faces. Conductive ink is then spread on this face so as to fill the gap formed by the plating mask. To obtain a uniform distribution of the conductive ink and then gel it, the conductive ink is preferably heated. A dielectric layer is applied on the conductive ink layer and the polymerization process is ended to obtain a strong adhesion between these two layers. In a preferred embodiment, conductive tracks are simultaneously designed on the other face of the base substrate to reduce thermo-mechanical strains and deformations.

摘要翻译： 公开了一种将防篡改层和分立元件嵌入到印刷电路板叠层中的方法。 根据该方法，将电镀掩模施加在基底基板上以部分地覆盖其一个面。 然后在该表面上扩散导电油墨，以填充由电镀掩模形成的间隙。 为了获得导电油墨的均匀分布，然后使其凝胶化，优选加热导电油墨。 在导电油墨层上施加电介质层，结束聚合过程，以获得这两层之间的强粘合性。 在优选实施例中，导电轨道同时设计在基底基板的另一面上，以减少热机械应变和变形。

公开(公告)号：US20150092939A1

公开(公告)日：2015-04-02

申请号：US14040337

申请日：2013-09-27

申请人： Kevin Gotze ,  Gregory Iovino ,  David Johnston ,  Patrick Koeberl ,  Jiangtao Li ,  Wei Wu

发明人： Kevin Gotze ,  Gregory Iovino ,  David Johnston ,  Patrick Koeberl ,  Jiangtao Li ,  Wei Wu

IPC分类号： H04L9/34

CPC分类号： H04L9/34 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

摘要： Embodiments of an invention for using dark bits to reduce physically unclonable function (PUF) error rates are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and dark bit logic. The PUF cell array is to provide a raw PUF value. The dark bit logic is to select PUF cells to mark as dark bits and to generate a dark bit mask based on repeated testing of the PUF cell array.

摘要翻译： 公开了使用暗位来减少物理不可克隆功能（PUF）错误率的发明的实施例。 在一个实施例中，集成电路包括PUF单元阵列和暗位逻辑。 PUF单元阵列是提供原始PUF值。 暗位逻辑是基于PUF单元阵列的重复测试来选择PUF单元来标记为暗位并产生暗位掩码。