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    METHOD OF EMBEDDING TAMPER PROOF LAYERS AND DISCRETE COMPONENTS INTO PRINTED CIRCUIT BOARD STACK-UP
    1.
    发明申请
    METHOD OF EMBEDDING TAMPER PROOF LAYERS AND DISCRETE COMPONENTS INTO PRINTED CIRCUIT BOARD STACK-UP 有权
    嵌入式防篡改层的方法和

    公开(公告)号：US20060086534A1

    公开(公告)日：2006-04-27

    申请号：US11163609

    申请日：2005-10-25

    申请人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic ,  Kevin Gotze ,  Tamas Visegrady

    发明人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic ,  Kevin Gotze ,  Tamas Visegrady

    IPC分类号： H05K1/11 ,  H01R12/04

    CPC分类号： H05K3/1258 ,  H05K1/0275 ,  H05K1/095 ,  H05K1/167 ,  H05K3/108 ,  H05K3/28 ,  H05K2201/10151 ,  H05K2203/0568 ,  Y10T29/49155

    摘要： A method for embedding tamper proof layers and discrete components into a printed circuit board stack-up is disclosed. According to this method, a plating mask is applied on a base substrate to cover partially one of its faces. Conductive ink is then spread on this face so as to fill the gap formed by the plating mask. To obtain a uniform distribution of the conductive ink and then gel it, the conductive ink is preferably heated. A dielectric layer is applied on the conductive ink layer and the polymerization process is ended to obtain a strong adhesion between these two layers. In a preferred embodiment, conductive tracks are simultaneously designed on the other face of the base substrate to reduce thermo-mechanical strains and deformations.

    摘要翻译： 公开了一种将防篡改层和分立元件嵌入到印刷电路板叠层中的方法。 根据该方法，将电镀掩模施加在基底基板上以部分地覆盖其一个面。 然后在该表面上扩散导电油墨，以填充由电镀掩模形成的间隙。 为了获得导电油墨的均匀分布，然后使其凝胶化，优选加热导电油墨。 在导电油墨层上施加电介质层，结束聚合过程，以获得这两层之间的强粘合性。 在优选实施例中，导电轨道同时设计在基底基板的另一面上，以减少热机械应变和变形。

    TAMPER-PROOF CAPS FOR LARGE ASSEMBLY
    2.
    发明申请
    TAMPER-PROOF CAPS FOR LARGE ASSEMBLY 失效
    用于大型组装的防篡改剂

    公开(公告)号：US20070038865A1

    公开(公告)日：2007-02-15

    申请号：US11460329

    申请日：2006-07-27

    申请人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic

    发明人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic

    IPC分类号： H04L9/00

    CPC分类号： G06F21/87 ,  H01L23/576 ,  H01L2224/16225 ,  H01L2924/15156 ,  H01L2924/3025 ,  H05K1/0275 ,  H05K1/141 ,  H05K2201/0715 ,  H05K2201/10151 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49172 ,  Y10T29/49174

    摘要： A tamper-proof cap adapted to be mounted on a large assembly for shielding a selected area of the large assembly is disclosed. The tamper-proof cap comprises a laminate stack-up structure wherein at least one open chamber is formed. The stack-up structure comprises at least two layers wherein tamper-proof layers are formed on top of the open chamber. A plurality of vias are disposed around the open chamber, forming with said tamper proof layers a tamper-proof structure around said open chamber. The vias are adapted for connecting the tamper-proof layers to the large assembly when the tamper-proof cap is mounted. In a preferred embodiment, the tamper-proof cap further comprises a shielding layer on top of the tamper-proof layer that are preferably done using conductive ink.

    摘要翻译： 公开了一种适于安装在大型组件上用于屏蔽大组件的选定区域的防篡改盖。 防破坏盖包括层压叠层结构，其中形成至少一个开放室。 堆叠结构包括至少两层，其中在敞开室的顶部上形成防篡改层。 多个通孔设置在开放室周围，与所述防篡改层一起形成围绕所述开放室的防篡改结构。 当安装防盗盖时，通孔适于将防篡改层连接到大组件。 在优选实施例中，防篡改帽还包括防篡改层顶部的屏蔽层，其优选地使用导电油墨进行。

    Structure of stacked vias in multiple layer electronic device carriers
    6.
    发明申请
    Structure of stacked vias in multiple layer electronic device carriers 有权
    多层电子设备载体中堆叠通孔的结构

    公开(公告)号：US20050156319A1

    公开(公告)日：2005-07-21

    申请号：US10515511

    申请日：2003-04-18

    申请人： Stefano Oggioni ,  Michele Castriotta ,  Gianluca Rogiani ,  Mauro Spreafico ,  Giorgio Viero

    发明人： Stefano Oggioni ,  Michele Castriotta ,  Gianluca Rogiani ,  Mauro Spreafico ,  Giorgio Viero

    IPC分类号： H05K3/46 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H01L23/48

    CPC分类号： H05K1/0251 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/0979 ,  H01L2924/00

    摘要： A stacked via structure (200) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks (205a, 205b, 205c) belonging to three adjacent conductive layers (110a, 110b, 110c) separated by dielectric layers (120), aligned according to z axis. Connections between these conductive tracks are done with at least two vias (210, 215) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis. In a preferred embodiment, the shape of these aligned conductive tracks looks like a disk or an annular ring and four vias are used to connect two adjacent conductive layers. These four vias are symmetrically disposed on each of said conductive track. The position of the vias between a first and a second adjacent conductive layers and between a second and a third adjacent conductive layers forms an angle of 45° according to z axis.

    摘要翻译： 公开了一种适于通过电子设备载体的导电层传输高频信号或高强度电流的堆叠通孔结构（200）。 叠置的通孔结构包括属于由电介质层（120）分开的根据z轴对准的三个相邻导电层（110a，110b，110c）的至少三个导电轨道（205a，205b，205c）。 这些导电轨道之间的连接通过在每个导电层之间的至少两个通孔（210,215）进行。 连接到导电轨道的一侧的通孔布置成使得它们不与根据z轴连接到另一侧的那些对准。 在优选实施例中，这些对准的导电轨迹的形状看起来像盘或环形环，并且四个通孔用于连接两个相邻的导电层。 这四个通孔对称地设置在每个导电轨道上。 在第一和第二相邻导电层之间以及第二和第三相邻导电层之间的通孔的位置根据z轴形成45°的角度。