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    Efficient multiplication, exponentiation and modular reduction implementations
    1.
    发明授权
    Efficient multiplication, exponentiation and modular reduction implementations 有权
    有效的乘法，乘法和模块化削减实现

    公开(公告)号：US09092645B2

    公开(公告)日：2015-07-28

    申请号：US13994782

    申请日：2011-12-05

    申请人： Erdinc Ozturk ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Deniz Karakoyunlu ,  Martin G. Dixon ,  Kahraman D. Akdemir

    发明人： Erdinc Ozturk ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Deniz Karakoyunlu ,  Martin G. Dixon ,  Kahraman D. Akdemir

    IPC分类号： H04L29/00 ,  G06F21/71 ,  H04L9/30

    CPC分类号： G06F21/71 ,  G06F7/723 ,  H04L9/3006 ,  H04L2209/12

    摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.

    摘要翻译： 在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是 指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

    EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS
    2.
    发明申请
    EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS 有权
    有效的实施，授权和模块化的减少实施

    公开(公告)号：US20150082047A1

    公开(公告)日：2015-03-19

    申请号：US13994782

    申请日：2011-12-05

    申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Deniz Karakoyunlu ,  Martin G. Dixon ,  Kahraman D. Akdemir

    发明人： Erdinc Ozturk ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Deniz Karakoyunlu ,  Martin G. Dixon ,  Kahraman D. Akdemir

    IPC分类号： G06F21/71 ,  H04L9/30

    CPC分类号： G06F21/71 ,  G06F7/723 ,  H04L9/3006 ,  H04L2209/12

    摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.

    摘要翻译： 在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是 指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

    Enhancing performance by instruction interleaving and/or concurrent processing of multiple buffers
    3.
    发明授权
    Enhancing performance by instruction interleaving and/or concurrent processing of multiple buffers 有权
    通过多个缓冲区的指令交织和/或并发处理来提高性能

    公开(公告)号：US08930681B2

    公开(公告)日：2015-01-06

    申请号：US12963298

    申请日：2010-12-08

    申请人： James D. Guilford ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Martin G. Dixon ,  Deniz Karakoyunlu ,  Kahraman D. Akdemir

    发明人： James D. Guilford ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Martin G. Dixon ,  Deniz Karakoyunlu ,  Kahraman D. Akdemir

    IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/48

    CPC分类号： G06F9/3851 ,  G06F9/30109 ,  G06F9/4843

    摘要： An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.

    摘要翻译： 实施例可以包括至少部分地执行第一指令列表和/或至少部分地执行第一和第二缓冲器的电路。 第一指令列表的执行可以至少部分地由第一函数调用的调用产生。 第一指令列表可以包括至少部分地与第三指令列表的至少一个其他部分交织的第二指令列表的至少一部分。 这些部分可以至少部分地由电路的一个或多个执行单元同时执行。 第二和第三指令列表可以至少部分地实现适合于通过单独的各自的功能调用来调用的相应算法。 并行处理可以至少部分地涉及互补算法。

    ENHANCING PERFORMANCE BY INSTRUCTION INTERLEAVING AND/OR CONCURRENT PROCESSING OF MULTIPLE BUFFERS
    4.
    发明申请
    ENHANCING PERFORMANCE BY INSTRUCTION INTERLEAVING AND/OR CONCURRENT PROCESSING OF MULTIPLE BUFFERS 有权
    通过指令交互和/或多个缓冲区的并发处理来提高性能

    公开(公告)号：US20120151183A1

    公开(公告)日：2012-06-14

    申请号：US12963298

    申请日：2010-12-08

    申请人： James D. Guilford ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Martin G. Dixon ,  Deniz Karakoyunlu ,  Kahraman D. Akdemir

    发明人： James D. Guilford ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Martin G. Dixon ,  Deniz Karakoyunlu ,  Kahraman D. Akdemir

    IPC分类号： G06F9/38 ,  G06F9/46

    CPC分类号： G06F9/3851 ,  G06F9/30109 ,  G06F9/4843

    摘要： An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.

    摘要翻译： 实施例可以包括至少部分地执行第一指令列表和/或至少部分地执行第一和第二缓冲器的电路。 第一指令列表的执行可以至少部分地由第一函数调用的调用产生。 第一指令列表可以包括至少部分地与第三指令列表的至少一个其他部分交织的第二指令列表的至少一部分。 这些部分可以至少部分地由电路的一个或多个执行单元同时执行。 第二和第三指令列表可以至少部分地实现适合于通过单独的各自的功能调用来调用的相应算法。 并行处理可以至少部分地涉及互补算法。

    SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION FOR MULTI-PRECISION ARITHMETIC
    6.
    发明申请
    SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION FOR MULTI-PRECISION ARITHMETIC 有权
    用于多精度算术的SIMD整数多项式累积指令

    公开(公告)号：US20140237218A1

    公开(公告)日：2014-08-21

    申请号：US13992728

    申请日：2011-12-19

    申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  James D. Guilford ,  Kirk S. Yap ,  Sean M. Gulley ,  wajdi K. Feghali ,  Martin G. Dixon

    发明人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  James D. Guilford ,  Kirk S. Yap ,  Sean M. Gulley ,  wajdi K. Feghali ,  Martin G. Dixon

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3001 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3893

    摘要： A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.

    摘要翻译： 乘法和累加（MAC）指令允许有效执行无符号整数乘法。 MAC指令表示作为第一操作数的第一向量寄存器，作为第二操作数的第二向量寄存器和作为目的地的第三向量寄存器。 第一向量寄存器存储第一因子，第二向量寄存器存储部分和。 执行MAC指令以将第一因子与隐式第二因子相乘以生成乘积，并将部分和添加到乘积以生成结果。 第一个因素，隐含的第二个因子和部分和具有相同的数据宽度，产品的数据宽度是两倍。 结果的最大一半存储在第三向量寄存器中，结果的最低有效半存储在第二向量寄存器中。