公开(公告)号：US20110122717A1

公开(公告)日：2011-05-26

申请号：US13017168

申请日：2011-01-31

申请人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

发明人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

IPC分类号： G11C29/04

CPC分类号： G11C29/848

摘要： Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.

摘要翻译： 提供控制器和存储器件。 在一个实施例中，控制器被配置为响应于接收来自存储器单元的存储器单元的缺陷列的地址，来代替存储器件的存储器单元的无缺陷列来代替存储器件的存储器单元的缺陷列 存储设备。 在另一个实施例中，存储器设备具有存储单元的列，并且被配置为接收寻址存储器件的存储器单元列序列的无缺陷列的存储器单元的外部地址，而不是缺陷存储器列 存储单元列的序列的单元，使得无缺陷列替代缺陷列。 无缺陷列是可用于替换缺陷列的列序列中的缺陷列之后的邻近无缺陷列。

公开(公告)号：US07881134B2

公开(公告)日：2011-02-01

申请号：US12272138

申请日：2008-11-17

申请人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

发明人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

IPC分类号： G11C29/00

CPC分类号： G11C29/848

摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells.

摘要翻译： 提供了操作存储器件的电子系统和方法。 在一个这样的实施例中，存储器装置接收外部地址，其代替存储器装置的存储器单元列的序列的不存在列的存储器单元的代替存储器列序列的存储器单元的缺陷列 使得无缺陷存储器列替换缺陷存储器列。 存储器单元的无缺陷列位于存储器单元列中的有缺陷列之后的存储器单元的缺陷列之后的非缺陷列，该存储器单元的列可用于替换存储单元的有缺陷的列。

公开(公告)号：US20100124132A1

公开(公告)日：2010-05-20

申请号：US12272138

申请日：2008-11-17

申请人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

发明人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/848

摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells.

摘要翻译： 提供了操作存储器件的电子系统和方法。 在一个这样的实施例中，存储器装置接收外部地址，其代替存储器装置的存储器单元列的序列的不存在列的存储器单元的代替存储器列序列的存储器单元的缺陷列 使得无缺陷存储器列替换缺陷存储器列。 存储器单元的无缺陷列位于存储器单元列中的有缺陷列之后的存储器单元的缺陷列之后的非缺陷列，该存储器单元的列可用于替换存储单元的缺陷列。

公开(公告)号：US20100124133A1

公开(公告)日：2010-05-20

申请号：US12274426

申请日：2008-11-20

申请人： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

发明人： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block.

摘要翻译： 提供了操作存储器件的电子系统和方法。 在一个这样的实施例中，存储器设备接收外部地址，其代替存储器块序列的缺陷存储器块来寻址存储器件的一系列存储器块的无缺陷存储器块，使得无缺陷存储器 块代替有缺陷的内存块。 在缺陷存储器块之后的无缺陷存储器块是可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的非缺陷存储块。

公开(公告)号：US08446787B2

公开(公告)日：2013-05-21

申请号：US12274426

申请日：2008-11-20

申请人： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

发明人： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

IPC分类号： G11C29/08

CPC分类号： G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block.

摘要翻译： 提供了操作存储器件的电子系统和方法。 在一个这样的实施例中，存储器设备接收外部地址，其代替存储器块序列的缺陷存储器块来寻址存储器件的一系列存储器块的无缺陷存储器块，使得无缺陷存储器 块代替有缺陷的内存块。 在缺陷存储器块之后的无缺陷存储器块是可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的非缺陷存储块。

公开(公告)号：US08295109B2

公开(公告)日：2012-10-23

申请号：US13017168

申请日：2011-01-31

申请人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

发明人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

IPC分类号： G11C29/00

CPC分类号： G11C29/848

摘要： Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.

摘要翻译： 提供控制器和存储器件。 在一个实施例中，控制器被配置为响应于接收来自存储器单元的存储器单元的缺陷列的地址，来代替存储器件的存储器单元的无缺陷列来代替存储器件的存储器单元的缺陷列 存储设备。 在另一个实施例中，存储器设备具有存储单元的列，并且被配置为接收寻址存储器件的存储器单元列序列的无缺陷列的存储器单元的外部地址，而不是缺陷存储器列 存储单元列的序列的单元，使得无缺陷列替代缺陷列。 无缺陷列是可用于替换缺陷列的列序列中的缺陷列之后的邻近无缺陷列。

公开(公告)号：US08611156B2

公开(公告)日：2013-12-17

申请号：US13550718

申请日：2012-07-17

申请人： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

发明人： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

IPC分类号： G11C11/34

CPC分类号： G06F3/0613 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C16/3459

摘要： Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.

摘要翻译： 公开了感测方法，编程方法，存储器件和存储器系统。 在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。 计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。 每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。 当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。 比较确定存储单元的状态。

公开(公告)号：US08243523B2

公开(公告)日：2012-08-14

申请号：US12720239

申请日：2010-03-09

申请人： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

发明人： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

IPC分类号： G11C11/34

CPC分类号： G06F3/0613 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C16/3459

摘要： Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.

摘要翻译： 公开了感测方法，编程方法，存储器件和存储器系统。 在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。 计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。 每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。 当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。 比较确定存储单元的状态。

公开(公告)号：US20120033504A1

公开(公告)日：2012-02-09

申请号：US13276359

申请日：2011-10-19

申请人： Vishal Sarin ,  Dzung H. Nguyen

发明人： Vishal Sarin ,  Dzung H. Nguyen

IPC分类号： G11C16/16

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/344

摘要： In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful.

摘要翻译： 在擦除存储器单元的存储块时，包含要擦除的存储块的半导体存储器可以以高的正电压被偏置。 构成存储块的存储单元的控制栅极可以用负电压偏置。 然后可以执行擦除验证以确定存储器块是否已被成功擦除。 如果存储块尚未被擦除，则可以重复以正电压偏置桶和具有负电压的控制栅的擦除操作，直到擦除验证成功。

公开(公告)号：US20100124126A1

公开(公告)日：2010-05-20

申请号：US12271223

申请日：2008-11-14

申请人： Vishal Sarin ,  Dzung H. Nguyen

发明人： Vishal Sarin ,  Dzung H. Nguyen

IPC分类号： G11C16/06 ,  G11C16/16 ,  G11C8/00

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/344

摘要： In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase verification can then be performed to determine if the memory block has been successfully erased. If the memory block has not been erased, the erase operation of biasing the tub with the positive voltage and the control gates with the negative voltage can be repeated until the erase verification is successful.

摘要翻译： 在擦除存储器单元的存储块时，包含要擦除的存储块的半导体存储器可以以高的正电压被偏置。 构成存储块的存储单元的控制栅极可以用负电压偏置。 然后可以执行擦除验证以确定存储器块是否已被成功擦除。 如果存储块尚未被擦除，则可以重复以正电压偏置桶和具有负电压的控制栅的擦除操作，直到擦除验证成功。