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    Fast lock scheme for phase locked loops and delay locked loops
    3.
    发明授权
    Fast lock scheme for phase locked loops and delay locked loops 有权
    用于锁相环和延迟锁定环的快速锁定方案

    公开(公告)号：US07466174B2

    公开(公告)日：2008-12-16

    申请号：US11396041

    申请日：2006-03-31

    申请人： Sridhar R. Tirumalai ,  Amir Bashir ,  Jing Li ,  Andrew M. Volk

    发明人： Sridhar R. Tirumalai ,  Amir Bashir ,  Jing Li ,  Andrew M. Volk

    IPC分类号： H03L7/06

    CPC分类号： H03L7/107 ,  H03L7/0893

    摘要： A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further apparatus, systems, and methods enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range.

    摘要翻译： 用于锁相环和延迟锁定环的快速锁定方案，其中装置，系统和方法包括在启动模式开始时使能的启动电路，并且在参考中的相变检测被禁用，并且将反馈信号反馈到 锁相环或延迟锁定环。 当检测到相变时，另外的装置，系统和方法使第一电荷泵能够在参考和反馈信号之间的相位差落在预定范围内时启用第二电荷泵。

    Address transition detection sensing interface for flash memory having multi-bit cells
    4.
    发明授权
    Address transition detection sensing interface for flash memory having multi-bit cells 失效
    具有多位单元的闪速存储器的地址转换检测传感接口

    公开(公告)号：US5594691A

    公开(公告)日：1997-01-14

    申请号：US389043

    申请日：1995-02-15

    申请人： Amir Bashir

    发明人： Amir Bashir

    IPC分类号： G11C11/56 ,  G11C13/00

    CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632

    摘要： An address transition detection interface is disclosed for a sensing circuit that determines a state of a memory cell having n possible states, where n is greater than 2, and wherein no decoding logic is required to translate outputs of comparators into binary bits. In the case where n is 4, the sensing circuit includes a first reference corresponding to a first threshold voltage level and a first comparator coupled to the memory cell and to the first reference. The first comparator compares a threshold voltage level of the memory cell to the first reference and provides a first result of the comparison as output. The sensing circuit further includes a second reference corresponding to a second threshold voltage level and a third reference corresponding to a third voltage level. A second comparator has one of its inputs coupled to the memory cell and its second input is selectively coupled to either the second reference or the third reference. A selector circuit selects between the second and third references in response to the first result. The selector circuit couples the second reference to the second comparator if the threshold voltage level of the memory cell is less than the first threshold voltage level. The selector circuit couples the third reference to the second comparator if the threshold voltage level of the memory cell is greater than the first voltage level. A forcing circuit provides the first reference to the second comparator in place of the second and third references for a predetermined period following the output of the first result by the first comparator and prior to the selective coupling to the second comparator by the selector circuit of the second reference or the third reference.

    摘要翻译： 公开了一种用于确定具有n个可能状态的存储单元的状态的感测电路的地址转换检测接口，其中n大于2，并且其中不需要解码逻辑来将比较器的输出转换为二进制位。 在n为4的情况下，感测电路包括对应于第一阈值电压电平的第一参考值和耦合到存储器单元和第一参考电压的第一比较器。 第一比较器将存储器单元的阈值电压电平与第一参考值进行比较，并将比较的第一结果提供为输出。 感测电路还包括对应于第二阈值电压电平的第二参考值和对应于第三电压电平的第三参考值。 第二比较器具有耦合到存储单元的其输入中的一个，其第二输入选择性地耦合到第二参考或第三参考。 选择器电路响应于第一结果在第二和第三参考之间进行选择。 如果存储器单元的阈值电压电平小于第一阈值电压电平，则选择器电路将第二参考电压耦合到第二比较器。 如果存储器单元的阈值电压电平大于第一电压电平，则选择器电路将第三参考电压耦合到第二比较器。 强制电路在第一比较器的第一结果输出之后的第一和第三参考值之间提供第二参考和第二参考，并且在通过选择器电路选择性耦合到第二比较器之前， 第二个参考或第三个参考。

    Fast lock scheme for phase locked loops and delay locked loops
    5.
    发明申请
    Fast lock scheme for phase locked loops and delay locked loops 有权
    用于锁相环和延迟锁定环的快速锁定方案

    公开(公告)号：US20070229127A1

    公开(公告)日：2007-10-04

    申请号：US11396041

    申请日：2006-03-31

    申请人： Sridhar Tirumalai ,  Amir Bashir ,  Jing Li ,  Andrew Volk

    发明人： Sridhar Tirumalai ,  Amir Bashir ,  Jing Li ,  Andrew Volk

    IPC分类号： H03L7/06

    CPC分类号： H03L7/107 ,  H03L7/0893

    摘要： A fast lock scheme for phase locked loops and delay locked loops, where an embodiment comprises a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further embodiments enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range. Other embodiments are described and claimed.

    摘要翻译： 用于锁相环和延迟锁定环的快速锁定方案，其中实施例包括在启动模式开始时使能的启动电路，并且在参考中的相变检测和对锁相环的反馈信号中被禁用，或者 延迟锁定环路。 当检测到相变时，另外的实施例使能第一电荷泵，并且当参考和反馈信号之间的相位差落在预定范围内时启用第二电荷泵。 描述和要求保护其他实施例。

    Power supply configured sensing scheme for flash EEPROM
    6.
    发明授权
    Power supply configured sensing scheme for flash EEPROM 失效
    闪存EEPROM的电源配置感应方案

    公开(公告)号：US5572465A

    公开(公告)日：1996-11-05

    申请号：US451037

    申请日：1995-05-25

    申请人： Amir Bashir

    发明人： Amir Bashir

    IPC分类号： G11C16/24 ,  G11C16/28 ,  G11C11/34

    CPC分类号： G11C16/28 ,  G11C16/24

    摘要： Bias selector circuitry for a memory cell sensing circuit is described. The bias selector circuitry includes a reference voltage generator, an output node, and a selector. The output node provides the bias voltage to the reference bitline load and the sense bitline load for controlling the reference and sense bitline node voltages, respectively. The selector provides a first bias voltage to the output node if a power supply voltage is at a first level. The selector selects the reference voltage generator to provide a second bias voltage to the output node if the power supply voltage is at a second level. The reference bitline node voltage is maintained at approximately the midpoint of the operating range of the sense bitline node voltage.

    摘要翻译： 描述了用于存储单元感测电路的偏置选择器电路。 偏置选择器电路包括参考电压发生器，输出节点和选择器。 输出节点分别为参考位线负载和感测位线负载提供偏置电压，用于分别控制参考电压和感测位线节点电压。 如果电源电压处于第一电平，则选择器向输出节点提供第一偏置电压。 如果电源电压处于第二电平，选择器选择参考电压发生器以向输出节点提供第二偏置电压。 参考位线节点电压保持在感测位线节点电压的工作范围的大约中点处。