利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

64 条记录 (耗时 0.03 秒)

    Apparatus and method for low latency power management on a serial data link
    3.
    发明授权
    Apparatus and method for low latency power management on a serial data link 有权
    串行数据链路上低延迟电源管理的装置和方法

    公开(公告)号：US07203853B2

    公开(公告)日：2007-04-10

    申请号：US10302295

    申请日：2002-11-22

    申请人： Andrew W. Martwick ,  Ken Drottar ,  David S. Dunning ,  Zale T. Schoenborn ,  Andrew M. Volk ,  Ronald W. Swartz ,  Dennis J. Miller

    发明人： Andrew W. Martwick ,  Ken Drottar ,  David S. Dunning ,  Zale T. Schoenborn ,  Andrew M. Volk ,  Ronald W. Swartz ,  Dennis J. Miller

    IPC分类号： G06F12/00

    CPC分类号： G06F1/3209 ,  G06F1/325 ,  G06F1/3253 ,  Y02D10/151

    摘要： An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.

    摘要翻译： 描述了串行数据链路上的低延迟功率管理的装置和方法。 在一个实施例中，该方法包括在电气空闲状态期间在接收机操作期间检测电空闲出口状况。 一旦检测到，则根据一个或多个接收到的数据同步训练模式执行数据同步。 最后，当在确定的同步重建周期内执行同步时，接收机将根据正常功率状态恢复操作。 因此，所描述的实施例示出了3GIO链路内的电源管理的开环低延迟功率恢复操作。

    Fast lock scheme for phase locked loops and delay locked loops
    4.
    发明授权
    Fast lock scheme for phase locked loops and delay locked loops 有权
    用于锁相环和延迟锁定环的快速锁定方案

    公开(公告)号：US07466174B2

    公开(公告)日：2008-12-16

    申请号：US11396041

    申请日：2006-03-31

    申请人： Sridhar R. Tirumalai ,  Amir Bashir ,  Jing Li ,  Andrew M. Volk

    发明人： Sridhar R. Tirumalai ,  Amir Bashir ,  Jing Li ,  Andrew M. Volk

    IPC分类号： H03L7/06

    CPC分类号： H03L7/107 ,  H03L7/0893

    摘要： A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further apparatus, systems, and methods enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range.

    摘要翻译： 用于锁相环和延迟锁定环的快速锁定方案，其中装置，系统和方法包括在启动模式开始时使能的启动电路，并且在参考中的相变检测被禁用，并且将反馈信号反馈到 锁相环或延迟锁定环。 当检测到相变时，另外的装置，系统和方法使第一电荷泵能够在参考和反馈信号之间的相位差落在预定范围内时启用第二电荷泵。

    Random number generator
    5.
    发明授权
    Random number generator 有权
    随机数发生器

    公开(公告)号：US08595274B2

    公开(公告)日：2013-11-26

    申请号：US11967716

    申请日：2007-12-31

    申请人： Pravas Pradhan ,  Andrew M. Volk ,  Praveen Dani

    发明人： Pravas Pradhan ,  Andrew M. Volk ,  Praveen Dani

    IPC分类号： G06F1/02

    CPC分类号： G06F7/588 ,  H04L9/0662 ,  H04L9/0861 ,  H04L2209/08 ,  H04L2209/12

    摘要： Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.

    摘要翻译： 通常，本公开描述了用于生成随机数的系统和方法。 在本文描述的至少一个实施例中，该方法可以包括经由集成电路根据至少一个安全应用产生随机比特，所述集成电路包括具有模拟核心的真随机数发生器。 该方法还可以包括经由内部产生的电源经由与所述真随机数发生器相关联的电压调节器向所述模拟核心提供电力。 当然，额外的操作也在本公开的范围内。

    SYNCHRONOUS FREQUENCY SYNTHESIZER
    6.
    发明申请
    SYNCHRONOUS FREQUENCY SYNTHESIZER 有权
    同步频率合成器

    公开(公告)号：US20100073035A1

    公开(公告)日：2010-03-25

    申请号：US12238189

    申请日：2008-09-25

    申请人： Praveen Dani ,  Robert Fulton ,  Andrew M. Volk ,  Surya Musunuri

    发明人： Praveen Dani ,  Robert Fulton ,  Andrew M. Volk ,  Surya Musunuri

    IPC分类号： H03B21/00

    CPC分类号： G06F1/08 ,  H03K5/1565 ,  H03K2005/00052 ,  H03L7/16

    摘要： An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

    摘要翻译： 提出了一种用于时钟生成的装置。 在一个实施例中，该装置包括相位插值器，其产生具有与两个输入时钟相关联的参考相位内的相位值的输出。 逻辑单元被耦合以确定相位内插器的多个相位设置。 分频器耦合到相位内插器，以基于可修改的分频器设置产生输出时钟。

    Circuitry and method to measure a duty cycle of a clock signal
    7.
    发明授权
    Circuitry and method to measure a duty cycle of a clock signal 有权
    测量时钟信号占空比的电路和方法

    公开(公告)号：US07479777B2

    公开(公告)日：2009-01-20

    申请号：US11648488

    申请日：2006-12-28

    申请人： Mukul Kelkar ,  Andrew M. Volk ,  Rajesh Kanakath ,  Vui Y. Liew

    发明人： Mukul Kelkar ,  Andrew M. Volk ,  Rajesh Kanakath ,  Vui Y. Liew

    IPC分类号： G06M1/10 ,  H03L7/00 ,  H03L7/08 ,  G01R25/00

    CPC分类号： G01R31/31727

    摘要： In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

    摘要翻译： 在一些实施例中，芯片包括用于产生时钟信号的时钟产生电路和参考信号振荡器电路，以产生具有比时钟信号更高的频率的参考信号。 芯片包括响应于参考信号变化而改变计数值的计数器; 以及计数逻辑电路，以使得计数存储电路响应于所述时钟信号中的至少一些变化来读取所述计数值，并且使所述计数存储电路中的至少一些值与所述时钟信号的占空比相关， 外部测试仪 描述和要求保护其他实施例。

    Method and apparatus for timing-dependant transfers using FIFOs
    8.
    发明授权
    Method and apparatus for timing-dependant transfers using FIFOs 失效
    使用FIFO进行定时相关传输的方法和装置

    公开(公告)号：US06928494B1

    公开(公告)日：2005-08-09

    申请号：US09538386

    申请日：2000-03-29

    申请人： Andrew M. Volk ,  Michael W. Williams ,  David J. McDonnell

    发明人： Andrew M. Volk ,  Michael W. Williams ,  David J. McDonnell

    IPC分类号： G11C7/10 ,  G06F3/00

    CPC分类号： G11C7/10

    摘要： A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different commands may be delivered through different FIFOs and can therefore have unpredictable arrival times with respect to each other, the delay and cueing information maintains the proper execution order and timing between the commands. Interactive control logic at the output of each FIFO uses the timing data to maintain execution in the proper order and with the proper inter-command delays.

    摘要翻译： 一种用于在两个不同时域之间传送命令和/或数据的方法和装置。 在一个实施例中，多个存储器命令以指定在不同命令的执行之间必须发生的延迟的方式被放置到一个或多个FIFO中。 与命令一起，将延迟信息放入FIFO中，指定执行命令和执行后续命令之间必须经过的时钟周期数量或其他形式的时间延迟。 该延迟信息用于在指定的时间段内延迟后续命令的执行，同时最小化或消除任何多余的延迟。 提示信息也可以放在FIFO中，其命令用于指定哪些命令在开始执行之前必须等待其他命令。 在启动传输的时域中确定和创建延迟和提示信息。 延迟和提示在其他时间域执行。 虽然不同的命令可以通过不同的FIFO传递，并且因此可以相对于彼此具有不可预测的到达时间，但延迟和提示信息保持命令之间的正确的执行顺序和定时。 每个FIFO的输出端的交互控制逻辑使用定时数据来维持正确顺序的执行和适当的指令间延迟。

    Buffer with compensating drive strength
    9.
    发明授权
    Buffer with compensating drive strength 有权
    具有补偿驱动强度的缓冲器

    公开(公告)号：US06624662B1

    公开(公告)日：2003-09-23

    申请号：US09608503

    申请日：2000-06-30

    申请人： Andrew M. Volk

    发明人： Andrew M. Volk

    IPC分类号： H03K19094

    CPC分类号： H03K19/0005 ,  H03K19/018585

    摘要： A compensating buffer providing both course tuning on initialization and fine-tuning during operation is disclosed. The course tuning is provided by a plurality of binary-weighted driver legs which are selected during initialization. The fine-tuning which is selectable during both initialization and during operation is provided through linear-weighted biasing. The linear-weighted biasing is simplified through the use of a digital-to-analog converter.

    摘要翻译： 公开了一种在操作期间提供初始化和微调两个过程调整的补偿缓冲器。 课程调整由在初始化期间选择的多个二进制加权的驾驶员腿提供。 在初始化和运行期间均可选择的微调通过线性加权偏置来提供。 通过使用数模转换器来简化线性加权偏置。