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1.发明申请INTEGRATED CIRCUIT CHIP INCORPORATING EMBEDDED THERMAL RADIATORS FOR LOCALIZED, ON-DEMAND, HEATING AND A SYSTEM AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT CHIP 失效集成电路芯片，用于本地化，点燃，加热和系统的嵌入式热分解器以及用于设计这种集成电路芯片的方法公开(公告)号：US20120168416A1
公开(公告)日：2012-07-05
申请号：US12984638
申请日：2011-01-05
CPC分类号： H05B1/0227 , G05D23/1934
摘要： Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.
摘要翻译： 公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。 芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。 温度传感器可以位于与TSZ相邻的半导体衬底中。 热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。 温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。 此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。 还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。
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2.发明授权Integrated circuit chip incorporating embedded thermal radiators for localized, on-demand, heating and a system and method for designing such an integrated circuit chip 失效集成电路芯片包含用于局部，点播，加热的嵌入式散热器，以及用于设计这种集成电路芯片的系统和方法公开(公告)号：US08756549B2
公开(公告)日：2014-06-17
申请号：US12984638
申请日：2011-01-05
CPC分类号： H05B1/0227 , G05D23/1934
摘要： Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.
摘要翻译： 公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。 芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。 温度传感器可以位于与TSZ相邻的半导体衬底中。 热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。 温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。 此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。 还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。
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公开(公告)号：US08304290B2
公开(公告)日：2012-11-06
申请号：US12642479
申请日：2009-12-18
IPC分类号： H01L21/00
CPC分类号： H05K3/3436 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/1146 , H01L2224/1147 , H01L2224/13012 , H01L2224/13014 , H01L2224/13082 , H01L2224/13083 , H01L2224/13116 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/1403 , H01L2224/14051 , H01L2224/141 , H01L2224/1413 , H01L2224/14133 , H01L2224/14135 , H01L2224/14179 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/814 , H01L2924/00011 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/3511 , H05K2201/09136 , H05K2201/094 , H05K2201/10674 , H05K2203/048 , Y02P70/613 , H01L2924/00014 , H01L2924/01028 , H01L2924/00012 , H01L2924/00 , H01L2224/81805
摘要： An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps.
摘要翻译： 公开了用于将集成电路器件连接到衬底的装置，系统和方法。 多个标准直径柱和三个或更多个增加直径的柱布置在集成电路装置上。 增加直径的支柱具有大于标准直径柱的直径和类似于标准直径柱的高度。 标准直径柱和增加的直径柱在集成电路器件上形成对应于与集成电路器件相对的衬底上的接触焊盘的图案。 第一组焊料凸点设置在标准直径柱和接触垫之间。 第二组焊料凸点设置在增加直径的支柱和接触垫之间。 第二组焊料凸块的预连接高度大于第一组焊料凸点的预连接高度。
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4.发明申请公开(公告)号：US20120216164A1
公开(公告)日：2012-08-23
申请号：US13032059
申请日：2011-02-22
IPC分类号： G06F17/50
CPC分类号： H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06051 , H01L2224/06179 , H01L2224/4813 , H01L2224/4911 , H01L2224/49171 , H01L2924/00014 , H01L2224/45099 , H01L2224/05599
摘要： Solutions for determining intra-die wirebond pad placement locations in an integrated circuit (IC) die are disclosed. In one embodiment, a method includes generating a dividing band in the IC die, the dividing band dividing the IC die into a first region and a second region; determining a voltage (IR) drop across the first region and the second region; comparing the IR drops across the regions; and in response to the IR drops being substantially unequal, moving the dividing band, determining new IR drops across the regions, and comparing the new IR drops until the IR drops are substantially equal. The dividing band may provide desired locations for intra-die wirebond pads.
摘要翻译： 公开了用于确定集成电路（IC）裸片中的管芯内焊盘放置位置的解决方案。 在一个实施例中，一种方法包括在IC管芯中产生分割带，将IC芯片划分成第一区域和第二区域; 确定穿过所述第一区域和所述第二区域的电压（IR）下降; 比较区域内的红细胞滴; 并且响应于IR滴基本上不相等，移动分割带，确定跨越该区域的新IR滴，并且比较新的IR滴直到IR下降基本相等。 分割带可为芯片内键合焊盘提供所需的位置。
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5.发明授权公开(公告)号：US08448118B2
公开(公告)日：2013-05-21
申请号：US13032059
申请日：2011-02-22
IPC分类号： G06F17/50
CPC分类号： H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06051 , H01L2224/06179 , H01L2224/4813 , H01L2224/4911 , H01L2224/49171 , H01L2924/00014 , H01L2224/45099 , H01L2224/05599
摘要： Solutions for determining intra-die wirebond pad placement locations in an integrated circuit (IC) die are disclosed. In one embodiment, a method includes generating a dividing band in the IC die, the dividing band dividing the IC die into a first region and a second region; determining a voltage (IR) drop across the first region and the second region; comparing the IR drops across the regions; and in response to the IR drops being substantially unequal, moving the dividing band, determining new IR drops across the regions, and comparing the new IR drops until the IR drops are substantially equal. The dividing band may provide desired locations for intra-die wirebond pads.
摘要翻译： 公开了用于确定集成电路（IC）裸片中的管芯内焊盘放置位置的解决方案。 在一个实施例中，一种方法包括在IC管芯中产生分割带，将IC芯片划分成第一区域和第二区域; 确定穿过所述第一区域和所述第二区域的电压（IR）下降; 比较区域内的红细胞滴; 并且响应于IR滴基本上不相等，移动分割带，确定跨越该区域的新IR滴，并且比较新的IR滴直到IR下降基本相等。 分割带可为芯片内键合焊盘提供所需的位置。
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公开(公告)号：US20110151627A1
公开(公告)日：2011-06-23
申请号：US12642479
申请日：2009-12-18
CPC分类号： H05K3/3436 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/1146 , H01L2224/1147 , H01L2224/13012 , H01L2224/13014 , H01L2224/13082 , H01L2224/13083 , H01L2224/13116 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/1403 , H01L2224/14051 , H01L2224/141 , H01L2224/1413 , H01L2224/14133 , H01L2224/14135 , H01L2224/14179 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/814 , H01L2924/00011 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/3511 , H05K2201/09136 , H05K2201/094 , H05K2201/10674 , H05K2203/048 , Y02P70/613 , H01L2924/00014 , H01L2924/01028 , H01L2924/00012 , H01L2924/00 , H01L2224/81805
摘要： An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps.
摘要翻译： 公开了用于将集成电路器件连接到衬底的装置，系统和方法。 多个标准直径柱和三个或更多个增加直径的柱布置在集成电路装置上。 增加直径的支柱具有大于标准直径柱的直径和类似于标准直径柱的高度。 标准直径柱和增加的直径柱在集成电路器件上形成对应于与集成电路器件相对的衬底上的接触焊盘的图案。 第一组焊料凸点设置在标准直径柱和接触垫之间。 第二组焊料凸点设置在增加直径的支柱和接触垫之间。 第二组焊料凸块的预连接高度大于第一组焊料凸点的预连接高度。
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