公开(公告)号：US20230352096A1

公开(公告)日：2023-11-02

申请号：US18348380

申请日：2023-07-07

申请人： WUXI ESIONTECH CO., LTD.

发明人： Zhengzhou CAO ,  Yueer SHAN ,  Bo TU ,  Xiaofei HE ,  Yanfei ZHANG ,  Zhenkai JI

IPC分类号： G11C16/10 ,  G11C16/04 ,  H03K19/017

CPC分类号： G11C16/102 ,  G11C16/0433 ,  H03K19/01721

摘要： A configuration control circuit of a flash-type FPGA capable of suppressing programming interference is provided. The configuration control circuit adds a programming selection circuit compared with a conventional configuration control circuit. When a programming operation is performed on a flash memory cell located in a target row and a target column, the programming selection circuit controls a path between a programming bit line (BL) voltage and a BL voltage obtaining terminal of the flash memory cell located in the target row and the target column to be turned on, and a path between the programming BL voltage and a BL voltage obtaining terminal of a flash memory cell located in another row and the target column to be turned off.

公开(公告)号：US20220116040A1

公开(公告)日：2022-04-14

申请号：US17645456

申请日：2021-12-22

申请人： WUXI ESIONTECH CO., LTD.

发明人： Yueer SHAN ,  Yanfeng XU ,  Xiaofei HE ,  Jicong FAN

IPC分类号： H03K19/173 ,  H03K3/037

摘要： A field-programmable gate array (FPGA) for using a configuration shift chain to implement a multi-bitstream function includes a bitstream control circuit, a multi-bitstream configuration shift chain and a configurable module. The FPGA enables multi-bitstream storage configuration bits to latch configuration bitstreams by adjusting a circuit structure of a multi-bitstream configuration shift chain in a combination of a control logic of a bitstream control circuit for the multi-bitstream configuration shift chain, and outputs one latched configuration bitstream from a configuration output terminal to a configurable module through each multi-bitstream storage configuration bit as required, so that the configurable module implements a logic function corresponding to the configuration bitstream outputted by the multi-bitstream configuration shift chain. By switching output of different configuration bitstreams, the FPGA can perform a plurality of times of high-speed switching to implement different logic functions without downloading bitstreams from an off-chip.