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1.发明授权Silicon germanium heterojunction bipolar transistor having interstitial trapping layer in base region 有权硅锗异质结双极晶体管在基极区域具有间隙捕获层公开(公告)号：US08299500B2
公开(公告)日：2012-10-30
申请号：US11161936
申请日：2005-08-23
IPC分类号： H01L29/737
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译： 异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。 外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。 外基的表面可以被硅化。
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公开(公告)号：US08853043B2
公开(公告)日：2014-10-07
申请号：US13610641
申请日：2012-09-11
IPC分类号： H01L21/331 , H01L21/8222 , H01L29/737 , H01L29/10 , H01L21/8249
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译： 异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。 外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。 外基的表面可以被硅化。
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公开(公告)号：US20130005108A1
公开(公告)日：2013-01-03
申请号：US13610641
申请日：2012-09-11
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译： 异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。 外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。 外基的表面可以被硅化。
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公开(公告)号：US20070051980A1
公开(公告)日：2007-03-08
申请号：US11161936
申请日：2005-08-23
申请人： Wade Hodge , Alvin Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley Orner
发明人： Wade Hodge , Alvin Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley Orner
IPC分类号： H01L29/737 , H01L21/8222
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译： 异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。 外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。 外基的表面可以被硅化。
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公开(公告)号：US07317215B2
公开(公告)日：2008-01-08
申请号：US10711482
申请日：2004-09-21
IPC分类号： H01L29/737
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.
摘要翻译： 在包括集电极区域的第一导电类型的半导体衬底中形成异质结双极晶体管。 在基板上形成基极区域，在基极区域上形成发射极区域。 集电极，基极和发射极区域中的至少一个包括掺杂有第一浓度的杂质的第一区域和掺杂有第二浓度的杂质的第二区域。 提高异质结双极晶体管的噪声性能和可靠性，而不会降低交流性能。
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6.发明授权公开(公告)号：US07538004B2
公开(公告)日：2009-05-26
申请号：US11937534
申请日：2007-11-09
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.
摘要翻译： 在包括集电极区域的第一导电类型的半导体衬底中形成异质结双极晶体管。 在基板上形成基极区域，在基极区域上形成发射极区域。 集电极，基极和发射极区域中的至少一个包括掺杂有第一浓度的杂质的第一区域和掺杂有第二浓度的杂质的第二区域。 提高异质结双极晶体管的噪声性能和可靠性，而不会降低交流性能。
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7.发明申请公开(公告)号：US20080124882A1
公开(公告)日：2008-05-29
申请号：US11937534
申请日：2007-11-09
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.
摘要翻译： 在包括集电极区域的第一导电类型的半导体衬底中形成异质结双极晶体管。 在基板上形成基极区域，在基极区域上形成发射极区域。 集电极，基极和发射极区域中的至少一个包括掺杂有第一浓度的杂质的第一区域和掺杂有第二浓度的杂质的第二区域。 提高异质结双极晶体管的噪声性能和可靠性，而不会降低交流性能。
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8.发明申请BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES 有权偏置控制深度底板噪声隔离集成电路设备结构公开(公告)号：US20110018094A1
公开(公告)日：2011-01-27
申请号：US12506270
申请日：2009-07-21
申请人： Phillip Francis Chapman , David Goren , Rajendran Krishnasamy , Benny Sheinman , Shlomo Shlafman , Raminderpal Singh , Wayne H. Woods
发明人： Phillip Francis Chapman , David Goren , Rajendran Krishnasamy , Benny Sheinman , Shlomo Shlafman , Raminderpal Singh , Wayne H. Woods
CPC分类号： H01L29/945 , H01L29/66181
摘要： A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques
摘要翻译： 一种用于在半导体芯片上的集成电路器件之间提供噪声隔离的新型有用的装置和方法。 本发明解决了由集成电路芯片中的数字开关器件产生的噪声的问题，该芯片可以通过硅衬底耦合到敏感的模拟电路（例如，PLL，收发器，ADC等）中，导致敏感模拟器的性能显着降低 电路。 本发明利用连接到地的深沟槽电容器（DTCAP）器件将受害电路与同一集成电路芯片上的侵扰器噪声源隔离开来。 与其他现有技术的屏蔽技术相比，电容器的深度穿透产生了深深的衬底中的接地屏蔽
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公开(公告)号：US07732845B2
公开(公告)日：2010-06-08
申请号：US12099339
申请日：2008-04-08
IPC分类号： H01L31/062
CPC分类号： H01L27/14603
摘要： A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region.
摘要翻译： 在CMOS图像传感器的栅电极上方形成拉伸应力产生结构，以在也是转移晶体管的源极区域的光电二极管的电荷收集阱和浮动漏极之间施加正常的拉伸应力 连接源极区域和浮动漏极的方向。 拉伸应力降低了源区域和转移晶体管的主体之间的势垒，以实现更快和更多地将源区域中的电荷转移到浮动漏极。 因此CMOS图像传感器中的图像滞后减少。 此外，由于施加到源极区域的正常拉伸应力，源极区域的充电容量也增强。
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公开(公告)号：US07652336B2
公开(公告)日：2010-01-26
申请号：US11834398
申请日：2007-08-06
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。 移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。 在衬套上形成填充材料。 填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。
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