公开(公告)号：US5058107A

公开(公告)日：1991-10-15

申请号：US293894

申请日：1989-01-05

Applicant: Wade J. Stone ,  Kikuo Ichiroku ,  Edwin A. Kelley ,  Don C. Devendorf

Inventor： Wade J. Stone ,  Kikuo Ichiroku ,  Edwin A. Kelley ,  Don C. Devendorf

IPC: H03D3/00 ,  H04B1/16 ,  H04J1/00 ,  H04J1/05

CPC classification number: H04J1/05

Abstract: A digital intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals including analog circuitry for receiving FDM signals and an analog-to-digital (A/D) converter for converting the received signals to a sampled digital received signal. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC). Digital low pass filtering isolates the desired channel centered at DC, and a digital complex mixer can be used to translate the isolated selected channel to a predetermined IF frequency. The in-phase portion of the digital IF centered selected channel or the DC centered complex envelope selected channel can then be provided to appropriate demodulation or decoder networks.

公开(公告)号：US5251218A

公开(公告)日：1993-10-05

申请号：US739593

申请日：1991-07-31

Applicant: Wade J. Stone ,  Kikuo Ichiroku ,  Edwin A. Kelley ,  Don C. Devendorf

Inventor： Wade J. Stone ,  Kikuo Ichiroku ,  Edwin A. Kelley ,  Don C. Devendorf

IPC: H04J1/05 ,  H04J1/00

CPC classification number: H04J1/05

Abstract: A digital radio frequency (RF) or intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals contained in a predetermined FDM band including an RF amplifier, an RF bandpass anti-alias filter, and an analog-to-digital (A/D) converter. The sample frequency F.sub.s of the A/D converter is lower than the lowest frequency in the predetermined FDM band and is selected to meet certain specified conditions based on the passband and stop band edges of the anti-alias filter so that the output of the A/D converter contains a non-distorted aliased frequency down converted digital version of the predetermined FDM band which is located between 0 Hz and one-half the sampling frequency. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC). Digital low pass filtering isolates the desired channel centered at DC, and a digital complex mixer can be used to translate the isolated selected channel to a predetermined IF frequency. The in-phase portion of the digital IF centered selected channel or the DC centered complex envelope selected channel can then be provided to appropriate demodulation or decoder networks.

Abstract translation: 一种用于频分复用（FDM）信号的数字射频（RF）或中频（IF）接收机，其包含在包括RF放大器，RF带通抗混叠滤波器和模数（A / D）转换器。 A / D转换器的采样频率Fs低于预定FDM频带中的最低频率，并且基于抗混叠滤波器的通带和阻带边缘被选择以满足某些特定条件，使得A / D转换器包含位于0Hz和采样频率的一半之间的预定FDM频带的非失真的混叠频率下变频数字版本。 响应于A / D转换器的数字输出的数字复合混频器将采样的数字接收信号的频谱转换为在零频率（DC）下使所需的FDM信道居中。 数字低通滤波将以DC为中心的期望信道隔离，并且数字复合混频器可用于将隔离的所选信道转换为预定的IF频率。 然后可以将数字IF居中选定信道或直流中心复信封选择信道的同相部分提供给适当的解调或解码器网络。

公开(公告)号：US5130578A

公开(公告)日：1992-07-14

申请号：US444454

申请日：1989-11-30

Applicant: Wade J. Stone ,  Edwin A. Kelley

Inventor： Wade J. Stone ,  Edwin A. Kelley

IPC: G06F7/02 ,  G06F7/22

CPC classification number: G06F9/30021 ,  G06F7/02 ,  G06F7/22

Abstract: The efficient high-speed N word comparator receives a plurality of digital inputs which are simultaneously compared by conducting a digital to analog conversion on each input signal and comparing the analog signals in a plurality of weighted analog comparators. Each comparator conducts a balance between an associated input signal and the remaining input signals providing an output indication if the associated signal is an extremum value. The outputs of the comparators are then encoded to provide an address of the digital input of the extremum value and to select the input value through a multiplexer. The address and the value are then provided to subsequent circuitry for processing. Simultaneous comparison of all signals provides significantly reduced ripple delay while reducing the requirements for hardware allowing monolithic implementation for a larger plurality of inputs.

Abstract translation: 有效的高速N字比较器接收多个数字输入，通过对每个输入信号进行数模转换，并对多个加权模拟比较器中的模拟信号进行比较，同时进行比较。 每个比较器在相关联的输入信号和剩余输入信号之间进行平衡，从而提供输出指示，如果相关联的信号是极值。 然后比较器的输出被编码以提供极值的数字输入的地址并通过多路复用器选择输入值。 然后将地址和值提供给后续电路进行处理。 所有信号的同时比较提供了显着降低的纹波延迟，同时减少了硬件的要求，允许对更大的多个输入进行单片实现。

公开(公告)号：US5729576A

公开(公告)日：1998-03-17

申请号：US641452

申请日：1996-04-30

Applicant: Wade J. Stone ,  Robert Tso ,  John M. Burns

Inventor： Wade J. Stone ,  Robert Tso ,  John M. Burns

IPC: G01S7/36 ,  G01S13/75 ,  H04B1/10 ,  H04L27/156 ,  H04L27/14 ,  H04B15/04

CPC classification number: G01S7/36 ,  G01S13/758 ,  H04B1/10 ,  H04L27/156

Abstract: A receiver used in a system having a transmitter (10) that sends an exciting signal to a remote transponder (18) is configured to receive a relatively weak signal from the transponder and to cancel out relatively high level interference from the transmission itself. A received frequency shift keying signal is fed to a tuned amplifier (22) for preliminary analog signal conditioning, and thence fed to an analog to digital converter (24). The output of the analog to digital converter is integrated (26) over a selected number of clock pulses and then dumped into a quarter rate quadrature demodulator (60) that multiplies the integrated signal by the same signal delayed by one clock interval. Undesired artifacts generated in the demodulator (60) are removed by a cascade of comb filters (70), and the demodulated digital output is available as the desired output of the receiver. The several clock signals of the system are all referenced from a basic exciter signal that itself gives rise to the transmitted interference signal so that the interference and all timing signals are approximately synchronous.

Abstract translation: 在具有向远程转发器（18）发送激励信号的发射机（10）的系统中使用的接收机被配置为从应答器接收相对较弱的信号，并且消除来自传输本身的相对较高级别的干扰。 接收的频移键控信号被馈送到用于初步模拟信号调理的调谐放大器（22），然后馈送到模数转换器（24）。 模数转换器的输出在选定数量的时钟脉冲上积分（26），然后转储成四分之一速率正交解调器（60），该积分解调器将积分信号乘以延迟一个时钟间隔的相同信号。 在解调器（60）中产生的不想要的伪影通过梳状滤波器（70）的级联去除，并且解调的数字输出可用作接收机的期望输出。 系统的几个时钟信号都来自基本的激励器信号，其本身引起发射的干扰信号，使得干扰和所有定时信号近似同步。

公开(公告)号：US5206647A

公开(公告)日：1993-04-27

申请号：US722763

申请日：1991-06-27

Applicant: Wade J. Stone

Inventor： Wade J. Stone

IPC: H03M1/18 ,  H03M1/20

CPC classification number: H03M1/208 ,  H03M1/183

Abstract: An automatically gain controlled multiple approximation analog to digital converter including a gain controlled amplifier responsive to the difference between an analog input signal and an analog version of a digital approximation of the analog input signal for providing a gain controlled analog residue signal, a quantizer for converting the gain controlled analog residue signal to a gain controlled digital residue signal, a digital divide circuit for dividing the gain controlled digital residue signal by a factor representative of the gain contained therein to provide a restored digital residue signal representative of the analog residue signal before it was amplified by the gain controlled amplifier, and a summing circuit for adding the restored digital residue signal and the digital approximation to provide the output of the gain controlled analog to digital converter. The gain controlled amplifier and the divide circuit are controlled by a gain control circuit that tends to maintain the output of the quantizer between first and second thresholds. Circuitry for providing the digital approximation of the analog input signal can include a linear predictor, or a sample and hold circuit and a coarse quantizer, for example.

Abstract translation: 一种自动增益控制的多重近似模数转换器，包括响应于模拟输入信号和模拟输入信号的数字近似的模拟版本之间的差异的增益控制放大器，用于提供增益控制的模拟残余信号，用于转换的量化器 增益控制的模拟残留信号到增益控制的数字残留信号，数字除法电路，用于将增益受控的数字残留信号除以表示其中所含的增益的因子，以提供代表其前的模拟残留信号的恢复的数字残留信号 由增益控制放大器放大，以及用于将恢复的数字残差信号和数字近似相加的求和电路，以提供增益受控模数转换器的输出。 增益控制放大器和除法电路由增益控制电路控制，该增益控制电路倾向于将量化器的输出保持在第一和第二阈值之间。 用于提供模拟输入信号的数字近似的电路可以包括例如线性预测器或采样保持电路和粗略量化器。

公开(公告)号：US5266952A

公开(公告)日：1993-11-30

申请号：US860528

申请日：1992-03-30

Applicant: Wade J. Stone ,  Howard S. Nussbaum ,  Kikuo Ichiroku ,  Benjamin Felder ,  William P. Posey

Inventor： Wade J. Stone ,  Howard S. Nussbaum ,  Kikuo Ichiroku ,  Benjamin Felder ,  William P. Posey

IPC: H03M1/08 ,  H03M1/10 ,  H03M1/20 ,  H03M1/40 ,  H03M3/02 ,  H03M1/12 ,  H03M3/04

CPC classification number: H03M1/208 ,  H03M1/1028

Abstract: A linear predictive ADC employs a fully feed forward design to extend its dynamic range, allow greater speed of operation, achieve stable operation and eliminate a requirement for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a subsequent value of the input signal. After conversion back to analog format, the predicted signal is compared with the actual subsequent value of the input signal to produce an error signal that is converted to a digital format by a second quantizer (Qf). The digital predicted signal is fed forward and combined with the digital error signal to produce a high precision digital output. The analog error signal is preferably amplified prior to digitation to take advantage of the full bit capacity of the second quanitzer (Qf), and then digitally de-amplified back to its original scale. Digital gain and offset adjustment mechanisms (44, 50) are preferably provided to compensate for amplification/de-amplification mismatches and system offsets. The quantizers (Qc, Qf), predictor (32) and a digital register (36) that interfaces between the predictor and the output combiner (46) are clocked in a set sequence to ensure that the predicted signal from the register (36) corresponds in time to the error signal presented to the output combiner (46).

Abstract translation: 线性预测ADC采用完全前馈设计来扩展其动态范围，允许更高的运行速度，实现稳定的运行，并且不需要采样和保持电路。 第一量化器（Qc）将输入模拟信号转换为数字格式，而信号预测器（32）预测输入信号的后续值。 在转换回模拟格式之后，将预测信号与输入信号的实际后续值进行比较，以产生由第二量化器（Qf）转换为数字格式的误差信号。 数字预测信号向前馈送并与数字误差信号组合以产生高精度数字输出。 模拟误差信号优选在数字化之前被放大，以利用第二quanitzer（Qf）的全部位容量，然后数字地放大回到其原始尺度。 优选地提供数字增益和偏移调整机构（44,50）以补偿放大/解除放大失配和系统偏移。 在预测器和输出组合器（46）之间接口的量化器（Qc，Qf），预测器（32）和数字寄存器（36）以设定序列计时，以确保来自寄存器（36）的预测信号对应 在时间上提供给输出组合器（46）的误差信号。

公开(公告)号：US4941153A

公开(公告)日：1990-07-10

申请号：US89281

申请日：1987-08-25

Applicant: Edwin A. Kelley ,  Wade J. Stone

Inventor： Edwin A. Kelley ,  Wade J. Stone

IPC: H03K17/60 ,  H03K19/018 ,  H04L25/02

CPC classification number: H04L25/02

Abstract: According to the invention, a high-speed digital data communication system employs current mode circuitry as input and output devices at the ends of a transmission line, such as the interconnections between integrated circuit chips. Specifically, a current mode driver switch generates output current amplitudes responsive to a source of a digital signal representative of data to be transmitted. The switch output is connected to the input of a transmission line. The output of the transmission line is connected to the input of a receiving circuit that responds to the current amplitudes and has an input at an approximately constant voltage level. The receiving circuit is a transistor connected in a common base configuration. The emitter of the transistor is connected to the output of the transmission line. The base of the transistor is connected to a constant voltage source. A pulse shaper in the form of a Schmitt trigger has positive feedback from output to input. The described current mode circuitry is incorporated into an integrated circuit chip.

Abstract translation: 根据本发明，高速数字数据通信系统采用电流模式电路作为传输线端部的输入和输出装置，例如集成电路芯片之间的互连。 具体地，电流模式驱动器开关响应于代表要发送的数据的数字信号的源产生输出电流幅度。 开关输出连接到传输线的输入。 传输线的输出连接到响应于当前幅度的接收电路的输入，并具有大致恒定的电压电平的输入。 接收电路是以共同的基本配置连接的晶体管。 晶体管的发射极连接到传输线的输出端。 晶体管的基极连接到恒压源。 施密特触发器形式的脉冲整形器具有从输出到输入的正反馈。 所描述的电流模式电路被并入到集成电路芯片中。