公开(公告)号：US20070001299A1

公开(公告)日：2007-01-04

申请号：US11531167

申请日：2006-09-12

申请人： Wataru KIKUCHI ,  Toshio SUGANO ,  Satoshi ISA

发明人： Wataru KIKUCHI ,  Toshio SUGANO ,  Satoshi ISA

IPC分类号： H01L23/34

CPC分类号： H01L23/5386 ,  H01L23/5383 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01055 ,  H01L2924/01068 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

摘要翻译： 堆叠的半导体封装包括两个半导体芯片（11,12），每个半导体芯片具有设置有以预定图案布置的多个芯片引脚的安装表面。 半导体芯片安装在基板（13）的相对表面上，使得安装表面通过基板相互面对。 基板设置有形成在除了芯片安装区域之外的区域中并且以与预定图案相同的图案布置的多个封装销。 半导体芯片的一对相应的芯片引脚通过使用长度相等的分支线连接到在其间的中间位置处形成的通孔。 通孔通过公共导线连接到与连接到通孔的芯片引脚对应的封装引脚。