公开(公告)号：US5598421A

公开(公告)日：1997-01-28

申请号：US390712

申请日：1995-02-17

申请人： Dan T. Tran ,  Wayne C. Datwyler ,  Long V. Ha

发明人： Dan T. Tran ,  Wayne C. Datwyler ,  Long V. Ha

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： The logic circuitry of an IC chip is connected to JTAG register chains which hold state information on each portion of the logic circuitry therein. A JTAG Tracker Module is connected to the controls of each of the JTAG register chains enabling a programmer-operator to read the present state of each JTAG register chain and enabling a readout of the logic circuits condition in a single clock period.

摘要翻译： IC芯片的逻辑电路连接到JTAG寄存器链，其保持逻辑电路的每个部分上的状态信息。 JTAG跟踪器模块连接到每个JTAG寄存器链的控制，使得编程器操作者可以读取每个JTAG寄存器链的当前状态，并且可以在单个时钟周期内读出逻辑电路条件。

公开(公告)号：US5553249A

公开(公告)日：1996-09-03

申请号：US400700

申请日：1995-03-08

申请人： Wayne C. Datwyler ,  Dan T. Tran ,  Long V. Ha

发明人： Wayne C. Datwyler ,  Dan T. Tran ,  Long V. Ha

IPC分类号： G06F12/08 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4013 ,  G06F13/4018 ,  G06F12/0804

摘要： A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds command, data and message registers, controlled by external logic, in an input channel pathway and an output channel pathway. The interface chip is basically limited to registers and multiplexers making it flexible for use in different architectures such as both Store-Through and Non-Store-Through cache protocols. In addition, such a simplified chip is simple to fabricate and to maintain free of defects.

摘要翻译： 单芯片数据路径门阵列接口将以第一时钟速率和单字协议操作的中央处理单元链接到以第二时钟速率和多字协议操作的双系统总线。 数据路径接口保持由外部逻辑控制的命令，数据和消息寄存器，在输入通道路径和输出通道路径中。 接口芯片基本上限于寄存器和多路复用器，使其灵活地用于不同架构，如存储直通和非存储缓存协议。 此外，这种简化的芯片制造简单，并且没有缺陷。

公开(公告)号：US5495573A

公开(公告)日：1996-02-27

申请号：US286855

申请日：1994-08-05

申请人： Wayne C. Datwyler ,  Long V. Ha ,  Dan T. Tran

发明人： Wayne C. Datwyler ,  Long V. Ha ,  Dan T. Tran

IPC分类号： G06F11/07 ,  G11C29/00

CPC分类号： G06F11/0772 ,  G06F11/0745

摘要： An error logging system where errors are captured on dual system busses operating at a lower clock rate (16 MHz) than the processor which receives the error information. The system functions to substantially reduce the loads on the processor in addition to maximizing the use of the system bus drivers which are pin-constrained. The processor operates at a higher clock rate (32 MHz). Processor commands to read error data from an error log register are synchronized down to the 16 MHz rate, then enabled onto a processor bus after a second synchronization operation back to the higher (32 MHz) rate. Provision is made for identifying several different types of error categories. An expandable error log register system is provided which uses selected bit positions to identify types of errors logged to the processor which also enables expansitivity for adding in future types of errors into the error logging system and renders compatibility for a processor operating at first clock rate with error data sensed at a second clock rate.

摘要翻译： 错误记录系统，其错误捕获在以比接收错误信息的处理器更低的时钟速率（16MHz）工作的双系统总线上。 除了最大限度地利用被引脚约束的系统总线驱动器之外，该系统还用于大大减少处理器上的负载。 处理器工作在更高的时钟频率（32 MHz）。 从错误日志寄存器读取错误数据的处理器命令被同步到16 MHz速率，然后在第二个同步操作回到较高（32 MHz）速率之后启用到处理器总线上。 提供了确定几种不同类型的错误类别。 提供了一种可扩展的错误日志寄存器系统，其使用所选择的位位置来识别记录到处理器的错误类型，该错误日志寄存器系统还能够扩展以将未来类型的错误添加到错误记录系统中，并且使得以第一时钟速率操作的处理器的兼容性与 以第二时钟速率感测的误差数据。

公开(公告)号：US08543838B1

公开(公告)日：2013-09-24

申请号：US12944025

申请日：2010-11-11

申请人： Siu-Hung Fred Au ,  Gregory Burd ,  Wayne C. Datwyler ,  Leonard J. Galasso ,  Tze Lei Poo ,  Minda Zhang

发明人： Siu-Hung Fred Au ,  Gregory Burd ,  Wayne C. Datwyler ,  Leonard J. Galasso ,  Tze Lei Poo ,  Minda Zhang

IPC分类号： G06F12/14

CPC分类号： G06F21/78 ,  G06F21/602 ,  G06F21/72 ,  G06F21/85

摘要： Cryptographic apparatus having corresponding methods and computer-readable media comprise: a mailbox memory module to store cryptographic commands received from a client over a client bus, wherein the client is external to the cryptographic apparatus; and a secure processor to obtain the cryptographic commands from the mailbox memory module over a first secure internal bus, execute the cryptographic commands, and store a status of execution of the cryptographic commands in the mailbox memory module over the first secure internal bus, wherein the client obtains the status of the cryptographic commands from the mailbox memory module over the client bus.

摘要翻译： 具有相应方法和计算机可读介质的加密设备包括：邮箱存储器模块，用于存储从客户端通过客户总线接收的加密命令，其中所述客户端在所述密码设备外部; 以及安全处理器，用于通过第一安全内部总线从所述邮箱存储器模块获得加密命令，执行所述加密命令，并且通过所述第一安全内部总线将所述密码命令的执行状态存储在所述邮箱存储器模块中，其中， 客户端通过客户端总线从邮箱内存模块获取加密命令的状态。

公开(公告)号：US5442754A

公开(公告)日：1995-08-15

申请号：US985662

申请日：1992-12-04

申请人： Wayne C. Datwyler ,  Paul B. Ricci

发明人： Wayne C. Datwyler ,  Paul B. Ricci

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： A system for controlling and routing messages and data received from dual system busses, through a bus interface unit, to a protocol translation logic means and to a processor in a central processing module connected onto a dual system bus network. The processor operates at a first clock rate and on a single-word communication protocol while the translation logic means operates at a second rate and multiple-word communication protocol. The processor and translation logic are destination modules which receive the benefit of the receiving control logic system. The receiving control logic system also services external modules on the system bus in order to receive data and control the routing of data to the destination modules. Destination modules which are busy and not ready will cause the system to inform the external transmitting modules that they must retry their transmission. The system also checks the quality of the data on the system busses and informs the processor when errors have been incurred, in addition to informing the originating modules when a transmitted message has been completed.

摘要翻译： 用于控制和路由从双系统总线接收的消息和数据通过总线接口单元传送到协议转换逻辑装置并连接到连接到双系统总线网络上的中央处理模块中的处理器的系统。 处理器以第一时钟速率和单字通信协议操作，而转换逻辑装置以第二速率和多字通信协议操作。 处理器和翻译逻辑是接收控制逻辑系统的好处的目标模块。 接收控制逻辑系统还为系统总线上的外部模块提供服务，以便接收数据并控制数据到目标模块的路由。 正在忙碌并且未准备好的目标模块将导致系统通知外部传输模块必须重试其传输。 该系统还检查系统总线上的数据质量，并在发生错误时通知处理器，以及在发送的消息已经完成时通知发端模块。

公开(公告)号：US07609468B2

公开(公告)日：2009-10-27

申请号：US11099746

申请日：2005-04-06

申请人： Daniel R Pinvidic ,  Wayne C. Datwyler ,  Hunardi Hudiono

发明人： Daniel R Pinvidic ,  Wayne C. Datwyler ,  Hunardi Hudiono

IPC分类号： G11B5/09

CPC分类号： G06F3/0659 ,  G06F3/0608 ,  G06F3/0676

摘要： A disk controller that controls data transfer between a storage device and a host system is provided. The disk controller includes logic having a state machine that controls de-assertion of a read gate signal based on sector size and/or whether a data segment is split or non-split. The read gate signal is de-asserted at programmable times, based on data sector size. The state machine interfaces with a register whose settings indicate to the state machine that next time when the state machine starts executing from an idle state it should process a second half of a split sector. The state machine also uses a register that to extend assertion of the read gate signal. It is noteworthy that the read gate signal is controlled on a positive and negative edge of a write clock signal.

摘要翻译： 提供了一种控制存储设备和主机系统之间的数据传输的磁盘控制器。 磁盘控制器包括具有状态机的逻辑，该状态机基于扇区大小和/或数据段是分裂还是非分割来控制读取门信号的断言。 基于数据扇区大小，读门信号在可编程时被取消置位。 状态机与设备向状态机指示下一次状态机从空闲状态开始执行的寄存器时，它将处理分割扇区的后半部分。 状态机还使用一个寄存器来扩展读门控信号的断言。 值得注意的是，读门信号被控制在写时钟信号的正和负沿。

公开(公告)号：US5444860A

公开(公告)日：1995-08-22

申请号：US837174

申请日：1992-02-14

申请人： Wayne C. Datwyler ,  Paul B. Ricci

发明人： Wayne C. Datwyler ,  Paul B. Ricci

IPC分类号： G06F5/10 ,  G06F5/06

CPC分类号： G06F5/10

摘要： A message transfer system between digital modules where two or more digital modules operate on separate and different message lengths and clock frequencies and where, temporary storage buffer (translator unit) holds messages being transferred between the different digital modules and acts as a speed matching and word length matching buffer unit to permit compatible transfer of message words. Also, the transfer system recognizes when requests are outstanding from both digital modules and can discard a message from a requesting module. Each of the two or more separate digital modules is serviced by dual system busses providing for redundancy of data transfer operations.

摘要翻译： 数字模块之间的消息传送系统，其中两个或多个数字模块在分离的和不同的消息长度和时钟频率上操作，并且其中临时存储缓冲器（转换器单元）保持在不同的数字模块之间传输的消息，并且作为速度匹配和字 长度匹配缓冲单元，以允许消息字的兼容传输。 此外，传送系统识别来自两个数字模块的请求何时未完成，并且可以从请求模块丢弃消息。 两个或多个单独的数字模块中的每一个由双系统总线提供服务，以提供数据传输操作的冗余。

公开(公告)号：US08023217B1

公开(公告)日：2011-09-20

申请号：US12603875

申请日：2009-10-22

申请人： Daniel R. Pinvidic ,  Wayne C. Datwyler ,  Hunardi Hudiono

发明人： Daniel R. Pinvidic ,  Wayne C. Datwyler ,  Hunardi Hudiono

IPC分类号： G11B5/09

CPC分类号： G06F3/0659 ,  G06F3/0608 ,  G06F3/0676

摘要： A device includes a data path configured to transfer data from a read channel device to a host. A read gate delay module is configured to receive a first read gate signal, to output a second read gate signal to the read channel device based on the first read gate signal, and selectively delay a transition of the second read gate signal between an asserted state and a non-asserted state based on a data sector size of a data segment and positive and negative edges of a write clock.

摘要翻译： 设备包括被配置为将数据从读通道设备传送到主机的数据路径。 读门延迟模块被配置为接收第一读门信号，以基于第一读门信号向读通道器件输出第二读门信号，并且选择性地延迟第二读门信号在被断言状态 以及基于数据段的数据扇区大小和写入时钟的正和负边缘的非断言状态。

公开(公告)号：US5509127A

公开(公告)日：1996-04-16

申请号：US985393

申请日：1992-12-04

申请人： Wayne C. Datwyler ,  Paul B. Ricci

发明人： Wayne C. Datwyler ,  Paul B. Ricci

IPC分类号： G06F13/36

CPC分类号： G06F13/36

摘要： A dual bus interface module, providing communication between a processor means and/or translation logic means and a set of dual system busses, provides a programmable transmit logic means which enables bus access for data transfer of commands and message transfer requests to destination modules on said system busses in a manner so as to use any available system bus to complete data transfer requests or to report the status of non-completed requests.

摘要翻译： 提供处理器装置和/或翻译逻辑装置和一组双系统总线之间的通信的双总线接口模块提供了一种可编程传输逻辑装置，该可编程传输逻辑装置使总线访问能够将命令和消息传送请求的数据传送到所述 系统总线，以便使用任何可用的系统总线完成数据传输请求或报告未完成请求的状态。

公开(公告)号：US5495585A

公开(公告)日：1996-02-27

申请号：US961744

申请日：1992-10-16

申请人： Wayne C. Datwyler ,  Paul B. Ricci

发明人： Wayne C. Datwyler ,  Paul B. Ricci

IPC分类号： G06F13/36 ,  G06F13/40

CPC分类号： G06F13/36 ,  G06F13/405

摘要： A programmable timing logic system for enabling access to a first or second bus, of dual system busses, by a central processor and/or a protocol-timing translation logic unit wherein messages may be received from one bus while command/control data is being transmitted to the other bus. Incomplete command cycles are retried a specific number "n" of times, each for a preset predetermined time period of "p" microseconds.

摘要翻译： 一种可编程定时逻辑系统，用于由中央处理器和/或协议定时转换逻辑单元访问双系统总线的第一或第二总线，其中可以在正在发送命令/控制数据的同时从一个总线接收消息 到另一辆公交车。 不完整的命令循环将重试特定数量的“n”次，每次为预设的预设时间段“p”微秒。