公开(公告)号：US07746698B2

公开(公告)日：2010-06-29

申请号：US11956032

申请日：2007-12-13

申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/12

摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

公开(公告)号：US20090154246A1

公开(公告)日：2009-06-18

申请号：US11956032

申请日：2007-12-13

申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/12

摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

公开(公告)号：US20090146201A1

公开(公告)日：2009-06-11

申请号：US11953690

申请日：2007-12-10

申请人： Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Ashot Melik-Martirosian

发明人： Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Ashot Melik-Martirosian

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  G11C16/0441 ,  G11C16/0491 ,  H01L29/42324 ,  H01L29/7781 ,  H01L29/7883

摘要： A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.

摘要翻译： 一种由多个存储单元组成的存储器件，每个存储器单元可以分别包括形成在隧道势垒之下并与每个存储单元的栅极氧化层相邻的底切区域中的多个电荷存储元件。 隧道势垒可以由诸如P +多晶硅或P型金属的高功函材料和/或高K材料形成。 通过采用这种隧道势垒，存储器单元可以降低在Fowler-Nordheim擦除期间栅极电子注入通过栅电极并进入电荷存储元件的可能性。 提供了制造具有至少一个这样的存储单元的存储器件的系统和方法。

公开(公告)号：US07659569B2

公开(公告)日：2010-02-09

申请号：US11953690

申请日：2007-12-10

申请人： Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Ashot Melik-Martirosian

发明人： Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Ashot Melik-Martirosian

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  G11C16/0441 ,  G11C16/0491 ,  H01L29/42324 ,  H01L29/7781 ,  H01L29/7883

摘要： A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.

摘要翻译： 一种由多个存储单元组成的存储器件，每个存储器单元可以分别包括形成在隧道势垒之下并与每个存储单元的栅极氧化层相邻的底切区域中的多个电荷存储元件。 隧道势垒可以由诸如P +多晶硅或P型金属的高功函材料和/或高K材料形成。 通过采用这种隧道势垒，存储器单元可以降低在Fowler-Nordheim擦除期间栅极电子注入通过栅电极并进入电荷存储元件的可能性。 提供了制造具有至少一个这样的存储单元的存储器件的系统和方法。

公开(公告)号：US07666739B2

公开(公告)日：2010-02-23

申请号：US11614048

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/792

摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

公开(公告)号：US08076712B2

公开(公告)日：2011-12-13

申请号：US12840165

申请日：2010-07-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07767517B2

公开(公告)日：2010-08-03

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L21/8242

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07696038B1

公开(公告)日：2010-04-13

申请号：US11412365

申请日：2006-04-26

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  G11C16/3418 ,  G11C16/3427

摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

摘要翻译： 提供了制造闪速存储器件的方法。 根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。 在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。 第一杂质掺杂区域形成在沟槽下面的衬底内。

公开(公告)号：US20080153222A1

公开(公告)日：2008-06-26

申请号：US11614048

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Sugimo Rinji ,  Wei Zheng

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/792

摘要： Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.

摘要翻译： 提供了用于制造分离电荷存储节点半导体存储器件的方法。 根据一个实施例，该方法包括以下步骤：在半导体衬底上形成具有第一物理厚度和第一有效氧化物厚度的栅极绝缘体层，并形成具有覆盖栅极绝缘体层的第一边缘和第二边缘的控制栅极电极 。 栅极绝缘体层被蚀刻以在控制栅电极的边缘处形成第一和第二底切区域，第一和第二底切区域各自暴露半导体衬底的一部分和控制栅电极的下侧部分。 第一和第二电荷存储节点形成在底切区域中，每个电荷存储节点包括具有基本上等于第一物理厚度的物理厚度和小于第一有效氧化物的有效氧化物厚度的氧化物存储材料 - 氧化物结构 厚度。

公开(公告)号：US20080149999A1

公开(公告)日：2008-06-26

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。