Patent search ap:("Wei-Bin Yang") AND inv:"Wei-Bin Yang" Page 1

1.

发明授权
Storage units and register file using the same 有权
Title translation: 存储单元和注册文件使用相同

公开(公告)号：US07577013B2

公开(公告)日：2009-08-18

申请号：US11232890

申请日：2005-09-23

Applicant: Wei-Bin Yang

Inventor： Wei-Bin Yang

IPC: G11C11/00

CPC classification number: G11C5/14

Abstract: A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a third inverter, in which the first and second inverters have different threshold voltages. The first inverter comprises an input terminal coupled to a write port and an output coupled to a read port. The second inverter comprises an input terminal coupled to the read port and an output terminal coupled to the write port. The third inverter comprises an input terminal coupled to the write port and an output terminal coupled to the read port.

Abstract translation: 一种能够在睡眠模式期间保留数据的存储单元。存储单元包括由第一和第二反相器组成的第一锁存器和由第一反相器和第三反相器构成的第二锁存器，其中第一和第二反相器具有不同的阈值电压。第一反相器包括耦合到写入端口的输入端子和耦合到读取端口的输出。第二反相器包括耦合到读端口的输入端和耦合到写端口的输出端。第三反相器包括耦合到写入端口的输入端子和耦合到读取端口的输出端子。

2.

发明授权
Divider 有权
Title translation: 分隔线

公开(公告)号：US07557621B2

公开(公告)日：2009-07-07

申请号：US11853819

申请日：2007-09-12

Applicant: Ting-Sheng Chao , Wei-Bin Yang , Yu-Lung Lo

Inventor： Ting-Sheng Chao , Wei-Bin Yang , Yu-Lung Lo

IPC: H03K23/00 , H03K21/00

CPC classification number: H03K23/544 , H03K3/356156

Abstract: A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.

Abstract translation: 提供一个分频器。分频器包括第一触发器，触发器阵列，第一NOT门，第二NOT门和电路。第一个触发器可以由一个频率信号触发。第一个非门耦合在最后一个第二触发器的正输出端和第一触发器之间。第二NOT门耦合在最后一个第二触发器的正输出端和电路之间。第一个非门和第二个非门由用于启用的模式控制信号控制。如果N是奇数，则电路包括线，如果N是偶数，则电路包括第三NOT门。

3.

发明申请
DYNAMIC FLOATING INPUT D FLIP-FLOP 有权
Title translation: 动态浮动输入D FLIP-FLOP

公开(公告)号：US20080106315A1

公开(公告)日：2008-05-08

申请号：US11615000

申请日：2006-12-22

Applicant: Ting-Sheng Jau , Wei-Bin Yang , Yu-Lung Lo

Inventor： Ting-Sheng Jau , Wei-Bin Yang , Yu-Lung Lo

IPC: H03K3/00

CPC classification number: H03K19/0963

Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.

Abstract translation: 提供动态浮动输入D触发器（DFIDFF）。 DFIDFF包括浮动输入级，第一串晶体管和第二串晶体管。在预充电期间，浮动输入级将输入数据发送到第一串晶体管; 第一串晶体管存储输入数据的逻辑状态，并将其输出节点预充电到第一级。在评估期间，第一串晶体管根据存储在第一晶体管串中的数据逻辑状态来决定其输出节点电平; 并且第二串晶体管根据第一串晶体管的输出节点的逻辑状态决定D触发器的输出电平。

4.

发明申请
Storage units and register file using the same 有权

公开(公告)号：US20060291320A1

公开(公告)日：2006-12-28

申请号：US11232890

申请日：2005-09-23

Applicant: Wei-Bin Yang

Inventor： Wei-Bin Yang

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a third inverter, in which the first and second inverters have different threshold voltages. The first inverter comprises an input terminal coupled to a write port and an output coupled to a read port. The second inverter comprises an input terminal coupled to the read port and an output terminal coupled to the write port. The third inverter comprises an input terminal coupled to the write port and an output terminal coupled to the read port.

5.

发明申请
DIVIDER 有权

公开(公告)号：US20080303562A1

公开(公告)日：2008-12-11

申请号：US11853819

申请日：2007-09-12

Applicant: Ting-Sheng Chao , Wei-Bin Yang , Yu-Lung Lo

Inventor： Ting-Sheng Chao , Wei-Bin Yang , Yu-Lung Lo

IPC: H03B19/12

CPC classification number: H03K23/544 , H03K3/356156

Abstract: A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.

Abstract translation: 提供一个分频器。分频器包括第一触发器，触发器阵列，第一NOT门，第二NOT门和电路。第一个触发器可以由一个频率信号触发。第一个非门耦合在最后一个第二触发器的正输出端和第一触发器之间。第二NOT门耦合在最后一个第二触发器的正输出端和电路之间。第一个非门和第二个非门由用于启用的模式控制信号控制。如果N是奇数，则电路包括线，如果N是偶数，则电路包括第三NOT门。

$Programmable fractional-N clock generators$

6.

发明授权
Programmable fractional-N clock generators 有权
Title translation: 可编程分数N时钟发生器

公开(公告)号：US07242231B2

公开(公告)日：2007-07-10

申请号：US11232949

申请日：2005-09-23

Applicant: Shu-Chang Kuo , Wei-Bin Yang , Kuo-Hsing Cheng

Inventor： Shu-Chang Kuo , Wei-Bin Yang , Kuo-Hsing Cheng

IPC: H03L7/06

CPC classification number: H03L7/0995 , H03K5/133 , H03K2005/00065 , H03L7/16

Abstract: Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D0˜Dm) with a first frequency (f0), in which the first clocks Di and Di-1 have a fixed phase difference and 1

Abstract translation: 时钟发生器能够根据二进制码产生不同频率的时钟。电压控制振荡模块以第一频率（f 0）产生多个第一时钟（D 0→D m），其中第一时钟D < i和D i-1具有固定的相位差和1

7.

发明授权
Dynamic floating input D flip-flop 有权
Title translation: 动态浮动输入D触发器

公开(公告)号：US07656211B2

公开(公告)日：2010-02-02

申请号：US11615000

申请日：2006-12-22

Applicant: Ting-Sheng Jau , Wei-Bin Yang , Yu-Lung Lo

Inventor： Ting-Sheng Jau , Wei-Bin Yang , Yu-Lung Lo

IPC: H03K3/00

CPC classification number: H03K19/0963

Abstract: A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of transistors; the first string of transistors stores the logic status of the input data, and pre-charges its output node to a first level. At an evaluation period, the first string of transistors decides its output node level in accordance with data logic status stored in the first string of transistors; and the second string of transistors decides output level of the D flip-flop in accordance with logic status of the output node of the first string of transistors.

Abstract translation: 提供动态浮动输入D触发器（DFIDFF）。 DFIDFF包括浮动输入级，第一串晶体管和第二串晶体管。在预充电期间，浮动输入级将输入数据发送到第一串晶体管; 第一串晶体管存储输入数据的逻辑状态，并将其输出节点预充电到第一级。在评估期间，第一串晶体管根据存储在第一晶体管串中的数据逻辑状态来决定其输出节点电平; 并且第二串晶体管根据第一串晶体管的输出节点的逻辑状态决定D触发器的输出电平。

8.

发明申请
Clock generators 有权
Title translation: 时钟发生器

公开(公告)号：US20060290392A1

公开(公告)日：2006-12-28

申请号：US11232949

申请日：2005-09-23

Applicant: Shu-chang Kuo , Wei-Bin Yang , Kuo-Hsing Cheng

Inventor： Shu-chang Kuo , Wei-Bin Yang , Kuo-Hsing Cheng

IPC: H03L7/06

CPC classification number: H03L7/0995 , H03K5/133 , H03K2005/00065 , H03L7/16

Abstract: Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D0˜Dm) with a first frequency (f0), in which the first clocks Di and Di−1 have a fixed phase difference and 1 B and A and B are positive integers.

Abstract translation: 时钟发生器能够根据二进制码产生不同频率的时钟。电压控制振荡模块以第一频率（f 0）产生多个第一时钟（D 0→D m），其中第一时钟D < i和D i-1具有固定的相位差和1 $1=A0，A> B和A和B是正整数。$

9.

发明申请
Low-power booth array multiplier with bypass circuits 审中-公开
Title translation: 低功率展位阵列乘法器，带旁路电路

公开(公告)号：US20060143260A1

公开(公告)日：2006-06-29

申请号：US11209664

申请日：2005-08-24

Applicant: Chuan-Cheng Peng , Wei-Bin Yang

Inventor： Chuan-Cheng Peng , Wei-Bin Yang

IPC: G06F7/52

CPC classification number: G06F7/5338

Abstract: A low-power Booth array multiplier with bypass circuits is provided. The multiplier includes a first encoder for Booth-encoding the multiplier; a second encoder for pre-encoding the multiplier to generate an enabling signal and a plurality of control signals, wherein the control signals are used for determining whether to process partial product calculations or not; a selector for generating partial products according to the encoding results from the first encoder and the multiplicand; an adder array, which is composed of a plurality of adders for summing up the partial products. The adder includes a first multiplexer and a second multiplexer. When an adder of one row is disabled by the enabling signal, the first multiplexer receives a summation of the former row and the second multiplexer receives the carry bit of the former row. The multiplier further includes a plurality of third multiplexers for outputting the summation of the adder array.

Abstract translation: 提供具有旁路电路的低功率布斯阵列乘法器。乘法器包括用于布尔编码乘法器的第一编码器; 用于对所述乘法器进行预编码以产生使能信号和多个控制信号的第二编码器，其中所述控制信号用于确定是否处理部分乘积运算; 用于根据来自第一编码器和被乘数的编码结果产生部分乘积的选择器; 加法器阵列，其由用于求和部分乘积的多个加法器组成。加法器包括第一多路复用器和第二多路复用器。当一行的加法器被使能信号禁用时，第一多路复用器接收前一行的求和并且第二多路复用器接收前一行的进位位。乘法器还包括用于输出加法器阵列的求和的多个第三多路复用器。