公开(公告)号：US20080010333A1

公开(公告)日：2008-01-10

申请号：US11776454

申请日：2007-07-11

申请人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

发明人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

IPC分类号： G06F7/52

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

公开(公告)号：US20070244954A1

公开(公告)日：2007-10-18

申请号：US11670357

申请日：2007-02-01

申请人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

发明人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

IPC分类号： G06F7/52

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit. The fused Booth encoder multiplexer unit, tree unit and adder unit function in a pipeline manner with the units operating on sequential data sets during a given processing cycle. The fused Booth encoder multiplexer unit may be advantageously laid out in a design of an integrated circuit chip with no gap present in the layout, which allows uniform wire length and avoids the necessity of large transistors to drive long interconnection wires.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。 融合的布尔编码器多路复用器单元，树形单元和加法器单元在给定的处理周期内以流水线方式与在顺序数据集上操作的单元进行功能。 融合布尔编码器多路复用器单元可有利地布置在集成电路芯片的设计中，布局中不存在间隙，这允许均匀的导线长度，并避免了大晶体管驱动长互连线的必要性。

公开(公告)号：US20050080834A1

公开(公告)日：2005-04-14

申请号：US10675674

申请日：2003-09-30

申请人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

发明人： Wendy Belluomini ,  Hung Ngo ,  Jun Sawada

IPC分类号： G06F7/52 ,  G06F7/544

CPC分类号： G06F7/5338 ,  G06F7/483 ,  G06F7/533 ,  G06F7/5443 ,  G06F2207/3872

摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit. The fused Booth encoder multiplexer unit, tree unit and adder unit function in a pipeline manner with the units operating on sequential data sets during a given processing cycle. The fused Booth encoder multiplexer unit may be advantageously laid out in a design of an integrated circuit chip with no gap present in the layout, which allows uniform wire length and avoids the necessity of large transistors to drive long interconnection wires.

摘要翻译： 乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。 融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器， 在输出节点维护该值。 编码器选择器单元并行操作以通常同时产生部分乘积位。 编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。 融合的布尔编码器多路复用器单元，树形单元和加法器单元在给定的处理周期内以流水线方式与在顺序数据集上操作的单元进行功能。 融合布尔编码器多路复用器单元可有利地布置在集成电路芯片的设计中，布局中不存在间隙，这允许均匀的导线长度，并避免了大晶体管驱动长互连线的必要性。

公开(公告)号：US20050102345A1

公开(公告)日：2005-05-12

申请号：US10702989

申请日：2003-11-06

申请人： Wendy Belluomini ,  Ramyanshu Datta ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

发明人： Wendy Belluomini ,  Ramyanshu Datta ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

IPC分类号： G06F7/50 ,  G06F7/60

CPC分类号： G06F7/607

摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.

摘要翻译： 一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。 进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。 第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。 由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。 此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

公开(公告)号：US20050102346A1

公开(公告)日：2005-05-12

申请号：US10702992

申请日：2003-11-06

申请人： Wendy Belluomini ,  Ramyanshu Datta ,  Jente Kuang ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

发明人： Wendy Belluomini ,  Ramyanshu Datta ,  Jente Kuang ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

IPC分类号： G06F7/50 ,  G06F7/60

CPC分类号： G06F7/607

摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

摘要翻译： 一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。 进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位 前一阶段 通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟 由高阶全加器。

公开(公告)号：US20070096770A1

公开(公告)日：2007-05-03

申请号：US11260571

申请日：2005-10-27

申请人： Ching-Te Chuang ,  Jente Kuang ,  Hung Ngo

发明人： Ching-Te Chuang ,  Jente Kuang ,  Hung Ngo

IPC分类号： H03K19/00

CPC分类号： G01R31/31725

摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

摘要翻译： 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

公开(公告)号：US20070082535A1

公开(公告)日：2007-04-12

申请号：US11608433

申请日：2006-12-08

申请人： Hung Ngo

发明人： Hung Ngo

IPC分类号： H01R13/627

CPC分类号： H01R13/6658 ,  H01R12/721 ,  H01R13/514 ,  H01R13/516 ,  H01R13/6215

摘要： An electrical connector may include a connector housing and a terminal tray. The terminal tray may include a tray body having a latch extending therefrom. The connector housing may define a latch receiving window. The latch and latch receiving window may be disposed such that the latch engages the latch receiving window only when the terminal tray is received in the housing in a preferred orientation. The terminal tray may include an electrically conductive contact having a board receiving end adapted to receive a printed circuit board and to exert sufficient pressure on the printed circuit board to retain the printed circuit board between the contact and the tray body. The connector may also include a plurality of cables bundled by a band, such as double-sided tape, such that respective portions of the cables are restrained from movement relative to one another.

摘要翻译： 电连接器可以包括连接器壳体和端子托盘。 端子盘可以包括具有从其延伸的闩锁的托盘主体。 连接器壳体可以限定闩锁接收窗口。 闩锁和闩锁接收窗口可以被布置成使得仅当终端托盘以优选的方向容纳在壳体中时，闩锁接合闩锁接收窗口。 端子托盘可以包括导电触点，其具有适于接收印刷电路板的板接收端并且在印刷电路板上施加足够的压力以将印刷电路板保持在接触件和托盘主体之间。 连接器还可以包括由诸如双面胶带的带捆绑的多个电缆，使得电缆的相应部分被限制为相对于彼此移动。

公开(公告)号：US20070061126A1

公开(公告)日：2007-03-15

申请号：US11219100

申请日：2005-09-01

申请人： Anthony Russo ,  Frank Chen ,  Mark Howell ,  Hung Ngo ,  Marcia Tsuchiya ,  David Weigand

发明人： Anthony Russo ,  Frank Chen ,  Mark Howell ,  Hung Ngo ,  Marcia Tsuchiya ,  David Weigand

IPC分类号： G06F9/455

CPC分类号： G06F3/03547 ,  G06F3/04883

摘要： The system and method of the present invention is directed to emulating and configuring any of a plurality of electronic input devices. A system in accordance with one embodiment of the present invention comprises an interface and an emulator. The interface is for selecting and configuring an electronic input device from a plurality of electronic input devices, and the emulator is for emulating the electronic input device. Preferably, the plurality of electronic input devices comprise any two or more of a scroll wheel, a mouse, a joy stick, a steering wheel, an analog button, and a touch bar. Also in a preferred embodiment, the interface is an Application Programming Interface (API) and the emulator comprises a finger swipe sensor for receiving user input.

摘要翻译： 本发明的系统和方法旨在仿真和配置多个电子输入设备中的任何一个。 根据本发明的一个实施例的系统包括接口和仿真器。 该接口用于从多个电子输入设备中选择和配置电子输入设备，并且该仿真器用于仿真电子输入设备。 优选地，多个电子输入装置包括滚轮，鼠标，操纵杆，方向盘，模拟按钮和触摸条中的任何两个或更多个。 同样在优选实施例中，接口是应用编程接口（API），并且仿真器包括用于接收用户输入的手指滑动传感器。

公开(公告)号：US20060103441A1

公开(公告)日：2006-05-18

申请号：US10988454

申请日：2004-11-12

申请人： Gary Carpenter ,  Alan Drake ,  Fadi Gebara ,  Chandler McDowell ,  Hung Ngo

发明人： Gary Carpenter ,  Alan Drake ,  Fadi Gebara ,  Chandler McDowell ,  Hung Ngo

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.

摘要翻译： 公开了一种校正数字信号占空比的电路和方法。 测量输入数字信号的占空比并将其与期望的占空比进行比较。 输入数字信号的前沿被传递到输出。 该电路和方法调节输出端的下降沿以达到所需的占空比。 响应于延迟版本的输入数字信号的上升沿发生下降沿。

公开(公告)号：US20060103431A1

公开(公告)日：2006-05-18

申请号：US10992486

申请日：2004-11-18

申请人： Hung Ngo ,  Jente Kuang ,  Harmander Deogun ,  AJ Kleinosowski

发明人： Hung Ngo ,  Jente Kuang ,  Harmander Deogun ,  AJ Kleinosowski

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  H03K19/0016

摘要： A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.

摘要翻译： 结合减少泄漏状态保持装置的动态逻辑电路降低了处理器和其他结合动态电路的系统的功耗。 保持器电路提供动态电路的输出级的状态的低泄漏保持，使得输出电路脚装置可以被禁用，除非在动态电路的输出中需要转换。 保持器电路包括具有比输出电路中的对应晶体管更小的面积的晶体管，从而当保持器电路保持输出并且输出电路脚器件被禁用时减小通过输出电路的栅极的泄漏。 可以通过延迟版本的动态逻辑门输出来提供输出电路脚装置的自定时控制，或者可以由产生预充电时钟的延迟版本或多周期信号的外部控制电路提供。