公开(公告)号：US07588983B2

公开(公告)日：2009-09-15

申请号：US12012593

申请日：2008-02-04

申请人： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoon ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-Tae Kim ,  Jeong-wook Han

发明人： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoon ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-Tae Kim ,  Jeong-wook Han

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

摘要翻译： 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的基板上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，分开形成第一漏极区域和第二浮动区域。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。

公开(公告)号：US07352026B2

公开(公告)日：2008-04-01

申请号：US10997835

申请日：2004-11-24

申请人： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

发明人： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

公开(公告)号：US20080132014A1

公开(公告)日：2008-06-05

申请号：US12012593

申请日：2008-02-04

申请人： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

发明人： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

摘要翻译： 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的基板上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，分开形成第一漏极区域和第二浮动区域。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。

公开(公告)号：US20050117443A1

公开(公告)日：2005-06-02

申请号：US10997835

申请日：2004-11-24

申请人： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

发明人： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC分类号： H01L27/115 ,  G11C8/02 ,  H01L21/8247

CPC分类号： H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

摘要翻译： 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的衬底上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，第一漏极区域和第二浮动区域彼此分开地形成。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。

公开(公告)号：US20080293200A1

公开(公告)日：2008-11-27

申请号：US12219995

申请日：2008-07-31

申请人： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

发明人： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

摘要翻译： 在非易失性半导体存储器件及其制造方法中，非易失性半导体存储器件包括半导体衬底中的单元掺杂区域和源极/漏极区域，该单元掺杂区域被掺杂为第一导电类型，沟道区域 设置在半导体衬底中的源极/漏极区之间，形成在电池掺杂区的上部的预定区域中的第一导电类型的隧道掺杂区，掺杂浓度高于 在隧道掺杂区域上形成在半导体衬底的表面上的隧道绝缘层，围绕隧道绝缘层并覆盖沟道区域的栅极绝缘层和暴露在隧道掺杂区域外的电池掺杂区域，以及 栅电极覆盖隧道绝缘层和栅极绝缘层。

公开(公告)号：US07364973B2

公开(公告)日：2008-04-29

申请号：US11882656

申请日：2007-08-03

申请人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

发明人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

IPC分类号： H01L21/8234

CPC分类号： H01L27/11266 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11293

摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

摘要翻译： 一种制造NOR型掩模ROM器件的方法包括在第一导电类型的半导体衬底上形成用于OFF电池的第一栅电极和用于ON电池的第二栅电极。 为了对掩模ROM器件进行编码，通过将与第一导电类型相反的第二导电类型的杂质注入到仅与第一栅电极的一侧相邻并且邻近第二侧的半导体衬底中来形成多个源极/漏极区域 的第二栅电极。 为了防止与接触区域的位线接触孔不对准，仅将额外的杂质注入到掩模ROM器件区域的位线接触区域中。 当形成在与掩模ROM器件相同的衬底上的半导体器件包括双扩散区域时，可以同时实现两者的附加注入。

公开(公告)号：US07253058B2

公开(公告)日：2007-08-07

申请号：US10899136

申请日：2004-07-27

申请人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

发明人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

IPC分类号： H01L21/8234

CPC分类号： H01L27/11266 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11293

摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

公开(公告)号：US20060006453A1

公开(公告)日：2006-01-12

申请号：US11099658

申请日：2005-04-06

申请人： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

发明人： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

摘要翻译： 在非易失性半导体存储器件及其制造方法中，非易失性半导体存储器件包括半导体衬底中的单元掺杂区域和源极/漏极区域，该单元掺杂区域被掺杂为第一导电类型，沟道区域 设置在半导体衬底中的源极/漏极区之间，形成在电池掺杂区的上部的预定区域中的第一导电类型的隧道掺杂区，掺杂浓度高于 在隧道掺杂区域上形成在半导体衬底的表面上的隧道绝缘层，围绕隧道绝缘层并覆盖沟道区域的栅极绝缘层和暴露在隧道掺杂区域外的电池掺杂区域，以及 栅电极覆盖隧道绝缘层和栅极绝缘层。

公开(公告)号：US20070275509A1

公开(公告)日：2007-11-29

申请号：US11882656

申请日：2007-08-03

申请人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

发明人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

IPC分类号： H01L21/8246

CPC分类号： H01L27/11266 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11293

摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

摘要翻译： 一种制造NOR型掩模ROM器件的方法包括在第一导电类型的半导体衬底上形成用于OFF电池的第一栅电极和用于ON电池的第二栅电极。 为了对掩模ROM器件进行编码，通过将与第一导电类型相反的第二导电类型的杂质注入到仅与第一栅电极的一侧相邻并且邻近第二侧的半导体衬底中来形成多个源极/漏极区域 的第二栅电极。 为了防止与接触区域的位线接触孔不对准，仅将额外的杂质注入到掩模ROM器件区域的位线接触区域中。 当形成在与掩模ROM器件相同的衬底上的半导体器件包括双扩散区域时，可以同时实现两者的附加注入。

公开(公告)号：US20050032288A1

公开(公告)日：2005-02-10

申请号：US10899136

申请日：2004-07-27

申请人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

发明人： Hyun-Khe Yoo ,  Weon-ho Park ,  Byoung-ho Kim

IPC分类号： H01L21/8234 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/112 ,  H01L21/336

CPC分类号： H01L27/11266 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11293

摘要： A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

摘要翻译： 一种制造NOR型掩模ROM器件的方法包括在第一导电类型的半导体衬底上形成用于OFF电池的第一栅电极和用于ON电池的第二栅电极。 为了对掩模ROM器件进行编码，通过将与第一导电类型相反的第二导电类型的杂质注入到仅与第一栅电极的一侧相邻并且邻近第二侧的半导体衬底中来形成多个源极/漏极区域 的第二栅电极。 为了防止与接触区域的位线接触孔不对准，仅将额外的杂质注入到掩模ROM器件区域的位线接触区域中。 当形成在与掩模ROM器件相同的衬底上的半导体器件包括双扩散区域时，可以同时实现两者的附加注入。