公开(公告)号：US20240329860A1

公开(公告)日：2024-10-03

申请号：US18224835

申请日：2023-07-21

申请人： Western Digital Technologies, Inc.

发明人： Shay Benisty ,  Ariel Navon ,  Alexander Bazarsky ,  Judah Gamliel Hahn

IPC分类号： G06F3/06

CPC分类号： G06F3/0625 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0679

摘要： A system and method are disclosed for flexible emergency power fail management for multiple persistent memory regions. In one embodiment, a method is provided that is performed in a host in communication with a plurality of data storage devices, each data storage device having a persistent memory region, wherein the host comprises a capacitor shared by the plurality of data storage devices. The method comprises determining an allocation of power from the capacitor to each of the plurality of data storage devices; and dynamically changing the allocation of power from the capacitor to at least one data storage device of the plurality of data storage devices. Other embodiments are disclosed.

公开(公告)号：US12093558B2

公开(公告)日：2024-09-17

申请号：US17751159

申请日：2022-05-23

申请人： Western Digital Technologies, Inc.

发明人： Ariel Navon ,  Idan Alrod ,  David Avraham ,  Eran Sharon ,  Vered Kelner

IPC分类号： G06F3/06

CPC分类号： G06F3/0653 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2212/7202

摘要： The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data “temperature” (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.

公开(公告)号：US12079635B2

公开(公告)日：2024-09-03

申请号：US17752264

申请日：2022-05-24

申请人： Western Digital Technologies, Inc.

发明人： Judah Gamliel Hahn ,  Shay Benisty ,  Alexander Bazarsky ,  Ariel Navon

IPC分类号： G06F9/4401 ,  G06F9/50

CPC分类号： G06F9/4403 ,  G06F9/4406 ,  G06F9/4408 ,  G06F9/441 ,  G06F9/5016 ,  G06F9/505 ,  G06F9/5061

摘要： A data storage device comprises a first memory, a second memory, and a controller. The first memory has a faster access time than the second memory. The controller is configured to store host-initialization code in the first memory, store a copy of the host-initialization code in the second memory, determine that the copy of the host-initialization code should be designated as the main version of the host-initialization code, and relocate the copy of the host-initialization code to the first memory, which makes the copy of the host-initialization code the main version of the host-initialization code that is accessed to boot-up the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US12067268B2

公开(公告)日：2024-08-20

申请号：US17838493

申请日：2022-06-13

申请人： Western Digital Technologies, Inc.

发明人： Gadi Vishne ,  Ariel Navon ,  David Avraham

IPC分类号： G06F3/06 ,  G06N20/00

CPC分类号： G06F3/0631 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06N20/00

摘要： A data storage device and method for dynamic prediction of random read with low memory consumption are provided. In one embodiment, a data storage device comprises a volatile memory, a non-volatile memory, and a controller. The controller is configured to allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory; determine an accuracy of the predicted next read commands; and based on the determined accuracy, dynamically allocate a different amount of space in the volatile memory for the history pattern matcher data structure. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US12038844B2

公开(公告)日：2024-07-16

申请号：US18104180

申请日：2023-01-31

申请人： Western Digital Technologies, Inc.

发明人： Opher Lieber ,  Ariel Navon ,  Alexander Bazarsky ,  Shay Benisty

IPC分类号： G06F12/0871 ,  G06F12/02 ,  G06F12/0893 ,  G06N20/00

CPC分类号： G06F12/0871 ,  G06F12/0246 ,  G06F12/0893 ,  G06N20/00 ,  G06F2212/214 ,  G06F2212/7205

摘要： A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.

公开(公告)号：US12008254B2

公开(公告)日：2024-06-11

申请号：US17182725

申请日：2021-02-23

申请人： Western Digital Technologies, Inc.

发明人： Ariel Navon ,  Shay Benisty

IPC分类号： G06F3/06 ,  G06F11/10

CPC分类号： G06F3/0641 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1076

摘要： Systems and methods for deduplication of storage device encoded data are described. The storage device may initiate a deduplication process and determine a encoded target data block and at least one encoded comparison data block. The storage device may compare the encoded target data block to the encoded comparison data blocks to determine similarity values. Based on the similarity values, the storage device may determine duplicate data units and eliminate extra duplicate data units.

公开(公告)号：US20240118736A1

公开(公告)日：2024-04-11

申请号：US17959037

申请日：2022-10-03

申请人： Western Digital Technologies, Inc.

发明人： Yoseph Hassan ,  Eran Sharon ,  Shay Benisty ,  Ariel Navon

IPC分类号： G06F1/3206

CPC分类号： G06F1/3206

摘要： Methods and apparatus for power management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine a power-per-processing event value for each of the set of processing engines based on total power consumption measurements, then control delivery of power to the processing engines based on the power-per-processing event values in accordance with a power budget. In some examples, the DSD employs a least-squares procedure to estimate the power-per-processing event values so the values can be determined without needing to measure the individual power consumption of the processing engines. Exemplary processing engines include a Read engine, a Write engine, etc. A recursive least-squares update procedure is also described.

公开(公告)号：US20230384971A1

公开(公告)日：2023-11-30

申请号：US17752305

申请日：2022-05-24

申请人： Western Digital Technologies, Inc.

发明人： Judah Gamliel Hahn ,  Ariel Navon ,  Shay Benisty

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/0656 ,  G06F3/0607 ,  G06F3/0679

摘要： A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US11755208B2

公开(公告)日：2023-09-12

申请号：US17499572

申请日：2021-10-12

申请人： Western Digital Technologies, Inc.

发明人： Ariel Navon ,  Alexander Bazarsky ,  Ofir Pele ,  Daniel Joseph Linnen

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06N3/08 ,  G06N3/045

CPC分类号： G06F3/0619 ,  G06F3/064 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G06N3/045 ,  G06N3/08 ,  G06F2212/7211

摘要： Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

公开(公告)号：US11734018B2

公开(公告)日：2023-08-22

申请号：US16932477

申请日：2020-07-17

申请人： Western Digital Technologies, Inc.

发明人： Shay Benisty ,  Judah Gamliel Hahn ,  Ariel Navon

IPC分类号： G06F9/44 ,  G06F9/4401 ,  G06F3/06 ,  G06F21/57 ,  G06F9/445

CPC分类号： G06F9/4403 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F21/575 ,  G06F9/445 ,  G06F2221/033

摘要： The present disclosure generally relates to reducing boot latency of memory devices in a dual boot system. The boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized.