公开(公告)号：US06489660B1

公开(公告)日：2002-12-03

申请号：US09862664

申请日：2001-05-22

申请人： Willem G. Einthoven ,  Lawrence LaTerza ,  Gary Horsman ,  Jack Eng ,  Danny Garbis

发明人： Willem G. Einthoven ,  Lawrence LaTerza ,  Gary Horsman ,  Jack Eng ,  Danny Garbis

IPC分类号： H01L2900

CPC分类号： H01L29/66121 ,  H01L29/8618

摘要： A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p-n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

摘要翻译： 具有对称电流 - 电压特性的双向瞬时电压抑制装置具有第一导电类型的下半导体层，第一导电类型的上半导体层和与下层和上层之间相邻并且设置在下层和上层之间的中间半导体层， 第二相反导电类型，使得形成上部和下部pn结。 中间层具有在接合点之间的中点处最高的净掺杂浓度。 此外，沿着垂直于下层，中层和上层的线的掺杂分布使得在中间层内，中间层的中心平面的一侧上的掺杂分布反映了相对侧上的掺杂分布。 此外，中间层的净掺杂浓度在接合点之间的距离的积分是这样的，当发生故障时，击穿是冲击破坏，而不是雪崩击穿。

公开(公告)号：US06602769B2

公开(公告)日：2003-08-05

申请号：US10264950

申请日：2002-10-04

申请人： Willem G. Einthoven ,  Lawrence LaTerza ,  Gary Horsman ,  Jack Eng ,  Danny Garbis

发明人： Willem G. Einthoven ,  Lawrence LaTerza ,  Gary Horsman ,  Jack Eng ,  Danny Garbis

IPC分类号： H02L2122

CPC分类号： H01L29/66121 ,  H01L29/8618

摘要： A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p−n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

摘要翻译： 具有对称电流 - 电压特性的双向瞬时电压抑制装置具有第一导电类型的下半导体层，第一导电类型的上半导体层和与下层和上层之间相邻并且设置在下层和上层之间的中间半导体层， 第二相反导电类型，使得形成上部和下部pn结。 中间层具有在接合点之间的中点处最高的净掺杂浓度。 此外，沿着垂直于下层，中层和上层的线的掺杂分布使得在中间层内，中间层的中心平面的一侧上的掺杂分布反映了相对侧上的掺杂分布。 此外，中间层的净掺杂浓度在接合点之间的距离的积分是这样的，当发生故障时，击穿是冲击破坏，而不是雪崩击穿。

公开(公告)号：US5882986A

公开(公告)日：1999-03-16

申请号：US50106

申请日：1998-03-30

申请人： Jack Eng ,  Joseph Y. Chan ,  Willem G. Einthoven ,  John E. Amato ,  Sandy Tan ,  Lawrence LaTerza ,  Gregory Zakaluk ,  Dennis Garbis

发明人： Jack Eng ,  Joseph Y. Chan ,  Willem G. Einthoven ,  John E. Amato ,  Sandy Tan ,  Lawrence LaTerza ,  Gregory Zakaluk ,  Dennis Garbis

IPC分类号： H01L29/06 ,  H01L21/301 ,  H01L21/304 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/3043

摘要： Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

摘要翻译： 从已知类型的半导体晶片开始，包括平行于晶片的主表面的内部平面p-n结，其中一个晶片表面被氮化硅掩蔽层覆盖。 然后通过掩模层锯切多个相交槽，以形成具有倾斜壁的多个台面，每个台面包括平面p-n结的一部分，其边缘与台面壁相交并暴露。 沟槽壁和暴露的接合边缘是玻璃封装在包括加热晶片的过程中。 然后在不需要图案化蚀刻剂掩模的选择性蚀刻工艺中去除掩模层，并且在台面顶部的现在暴露的硅表面以及晶片的相对表面是金属镀覆的。 然后将晶片沿着平面通过沟槽切割，以提供各自具有玻璃钝化台面的单个芯片。

公开(公告)号：US5360509A

公开(公告)日：1994-11-01

申请号：US21130

申请日：1993-03-08

申请人： Gregory Zakaluk ,  Dennis Garbis ,  Joseph Y. Chan ,  John Latza ,  Lawrence LaTerza

发明人： Gregory Zakaluk ,  Dennis Garbis ,  Joseph Y. Chan ,  John Latza ,  Lawrence LaTerza

IPC分类号： H01L21/20 ,  H01L21/304 ,  H01L21/306

CPC分类号： H01L21/304 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  Y10S438/959

摘要： Significant reductions in the cost of fabrication of epitaxial semiconductor devices without sacrifice of functional characteristics is achieved by eliminating the conventional but costly polishing procedure, instead subjecting the substrate to grinding, cleaning and etching processes in which the grinding removes material from the surface to a depth of at least 65 microns and the etching further removes material to a depth of about 6-10 microns, the grinding preferably being carried out in two steps, the first being a coarse step and the second being a fine step, with the rotated grinding elements dwelling at their respective last grinding positions for a short period of time. The result is the equivalent of the prior art polishing procedure which took considerably longer to carry out and which therefore was much more costly. Complementing this grinding procedure is an improved and cost effective epitaxial process utilizing a unique two-step hydrochloric gas high temperature etch and a faster growth rate process with shorter cycle steps. In addition, oxygen control and "gettering" capabilities result in a total process improving the economics of formation of epitaxial semiconductor devices.

摘要翻译： 通过消除常规但昂贵的抛光方法，可以显着降低外延半导体器件的制造成本，而不牺牲功能特性，而不是对基板进行研磨，清洗和蚀刻工艺，其中研磨将材料从表面移除到深度 至少65微米，并且蚀刻进一步将材料去除至约6-10微米的深度，研磨优选以两个步骤进行，第一步是粗步骤，第二步是精细步骤，旋转的研磨元件 住在他们各自的最后研磨位置很短的时间。 结果相当于现有技术的抛光程序，其花费相当长的时间来执行，因此成本更高。 补充该研磨程序是利用独特的两步盐酸气体高温蚀刻和具有较短循环步骤的更快生长速率工艺的改进且成本有效的外延工艺。 此外，氧气控制和“吸气”能力导致整个工艺改善外延半导体器件形成的经济性。