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    Low cost method of fabricating epitaxial semiconductor devices
    1.
    发明授权
    Low cost method of fabricating epitaxial semiconductor devices 失效
    制造外延半导体器件的低成本方法

    公开(公告)号：US5360509A

    公开(公告)日：1994-11-01

    申请号：US21130

    申请日：1993-03-08

    申请人： Gregory Zakaluk ,  Dennis Garbis ,  Joseph Y. Chan ,  John Latza ,  Lawrence LaTerza

    发明人： Gregory Zakaluk ,  Dennis Garbis ,  Joseph Y. Chan ,  John Latza ,  Lawrence LaTerza

    IPC分类号： H01L21/20 ,  H01L21/304 ,  H01L21/306

    CPC分类号： H01L21/304 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  Y10S438/959

    摘要： Significant reductions in the cost of fabrication of epitaxial semiconductor devices without sacrifice of functional characteristics is achieved by eliminating the conventional but costly polishing procedure, instead subjecting the substrate to grinding, cleaning and etching processes in which the grinding removes material from the surface to a depth of at least 65 microns and the etching further removes material to a depth of about 6-10 microns, the grinding preferably being carried out in two steps, the first being a coarse step and the second being a fine step, with the rotated grinding elements dwelling at their respective last grinding positions for a short period of time. The result is the equivalent of the prior art polishing procedure which took considerably longer to carry out and which therefore was much more costly. Complementing this grinding procedure is an improved and cost effective epitaxial process utilizing a unique two-step hydrochloric gas high temperature etch and a faster growth rate process with shorter cycle steps. In addition, oxygen control and "gettering" capabilities result in a total process improving the economics of formation of epitaxial semiconductor devices.

    摘要翻译： 通过消除常规但昂贵的抛光方法，可以显着降低外延半导体器件的制造成本，而不牺牲功能特性，而不是对基板进行研磨，清洗和蚀刻工艺，其中研磨将材料从表面移除到深度 至少65微米，并且蚀刻进一步将材料去除至约6-10微米的深度，研磨优选以两个步骤进行，第一步是粗步骤，第二步是精细步骤，旋转的研磨元件 住在他们各自的最后研磨位置很短的时间。 结果相当于现有技术的抛光程序，其花费相当长的时间来执行，因此成本更高。 补充该研磨程序是利用独特的两步盐酸气体高温蚀刻和具有较短循环步骤的更快生长速率工艺的改进且成本有效的外延工艺。 此外，氧气控制和“吸气”能力导致整个工艺改善外延半导体器件形成的经济性。

    Semiconductor chips having a mesa structure provided by sawing
    2.
    发明授权
    Semiconductor chips having a mesa structure provided by sawing 失效
    具有通过锯切提供的台面结构的半导体芯片

    公开(公告)号：US5882986A

    公开(公告)日：1999-03-16

    申请号：US50106

    申请日：1998-03-30

    申请人： Jack Eng ,  Joseph Y. Chan ,  Willem G. Einthoven ,  John E. Amato ,  Sandy Tan ,  Lawrence LaTerza ,  Gregory Zakaluk ,  Dennis Garbis

    发明人： Jack Eng ,  Joseph Y. Chan ,  Willem G. Einthoven ,  John E. Amato ,  Sandy Tan ,  Lawrence LaTerza ,  Gregory Zakaluk ,  Dennis Garbis

    IPC分类号： H01L29/06 ,  H01L21/301 ,  H01L21/304 ,  H01L21/30 ,  H01L21/46

    CPC分类号： H01L21/3043

    摘要： Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

    摘要翻译： 从已知类型的半导体晶片开始，包括平行于晶片的主表面的内部平面p-n结，其中一个晶片表面被氮化硅掩蔽层覆盖。 然后通过掩模层锯切多个相交槽，以形成具有倾斜壁的多个台面，每个台面包括平面p-n结的一部分，其边缘与台面壁相交并暴露。 沟槽壁和暴露的接合边缘是玻璃封装在包括加热晶片的过程中。 然后在不需要图案化蚀刻剂掩模的选择性蚀刻工艺中去除掩模层，并且在台面顶部的现在暴露的硅表面以及晶片的相对表面是金属镀覆的。 然后将晶片沿着平面通过沟槽切割，以提供各自具有玻璃钝化台面的单个芯片。

    Method for fabricating a multilayer epitaxial structure
    4.
    发明授权
    Method for fabricating a multilayer epitaxial structure 失效
    制造多层外延结构的方法

    公开(公告)号：US5432121A

    公开(公告)日：1995-07-11

    申请号：US242877

    申请日：1994-05-16

    申请人： Joseph Chan ,  Dennis Garbis ,  Lawrence Laterza ,  Gregory Zakaluk

    发明人： Joseph Chan ,  Dennis Garbis ,  Lawrence Laterza ,  Gregory Zakaluk

    IPC分类号： H01L21/22 ,  H01L21/20

    CPC分类号： H01L21/2205 ,  Y10S148/041

    摘要： An all epitaxial process performed entirely in a CVD reactor is employed to grow epitaxial layers with accurately controlled successively low and high dopant concentrations over a heavily doped substrate, eliminating the need for a separate diffusion, even for high purity concentrations. After purging the reactor system, the heavily doped silicon substrate is "capped" by growing two successive very thin silicon sublayers of the same conductivity type. The reactor chamber is subjected to a hydrogen purge to deplete any contaminents after each sublayer is formed. The cap sublayers form a narrow, abrupt intrinsic transition region with the substrate and become an active part of the device structure. A lightly doped epitaxial layer is grown over the "capped" substrate so that a depletion region can be formed in the device under suitable reverse bias. A heavily doped epitaxial layer is then grown over the lightly doped epitaxial layer. The heavily doped epitaxial layer forms a contact layer and has a polarity opposite to that of the substrate.

    摘要翻译： 采用在CVD反应器中完全执行的全部外延工艺来在重掺杂衬底上生长具有精确控制的连续低和高掺杂剂浓度的外延层，从而消除了对于高纯度浓度的单独扩散的需要。 在清洗反应器系统之后，通过生长相同导电类型的两个连续的非常薄的硅子层，重掺杂硅衬底被“封盖”。 在形成每个子层之后，对反应器室进行氢气净化以消除任何污染物。 帽子层与衬底形成窄的，突然的本征过渡区，并成为器件结构的有效部分。 在“封盖”衬底上生长轻掺杂的外延层，使得可以在合适的反向偏压下在器件中形成耗尽区。 然后在轻掺杂的外延层上生长重掺杂的外延层。 重掺杂的外延层形成接触层，并具有与衬底相反的极性。

    Method for fabricating a multilayer epitaxial structure
    5.
    发明授权
    Method for fabricating a multilayer epitaxial structure 失效
    制造多层外延结构的方法

    公开(公告)号：US5324685A

    公开(公告)日：1994-06-28

    申请号：US15384

    申请日：1993-02-09

    申请人： Reinhold Hirtz ,  Gregory Zakaluk ,  Joseph Chan ,  Dennis Garbis ,  Lawrence Laterza ,  Ali Salih

    发明人： Reinhold Hirtz ,  Gregory Zakaluk ,  Joseph Chan ,  Dennis Garbis ,  Lawrence Laterza ,  Ali Salih

    IPC分类号： H01L21/22 ,  H01L21/203

    CPC分类号： H01L21/2205 ,  Y10S438/902

    摘要： An all epitaxial process performed entirely in a CVD reactor is employed to grow heavily doped layer on lightly doped layer on a heavily doped substrate, eliminating the need for separate diffusion, even for high impurity concentrations. The process starts with a heavily doped silicon substrate of carrier concentration typically greater than 1.times.10.sup.19 per cm.sup.3. To minimize outdiffusion, the substrate is "capped" by growing very thin and heavily doped silicon layers which are depleted by hydrogen purges. A first epitaxial layer is grown over the "capped" substrate. This layer is relatively lightly doped, having a resistivity of more than 200 ohm.cm. A second epitaxial layer is then grown over the first epitaxial layer. The second epitaxial layer has a polarity opposite to that of the substrate and is heavily doped to a resistivity of less than 0.005 ohm cm.

    摘要翻译： 采用在CVD反应器中完全执行的全部外延工艺来在重掺杂衬底上的轻掺杂层上生长重掺杂层，即使对于高杂质浓度也无需分开扩散。 该过程从载流子浓度通常大于1×1019 / cm3的重掺杂硅衬底开始。 为了最小化扩散，通过生长非常薄且重掺杂的硅层，衬底被“封盖”，其被氢清除耗尽。 在“封盖”基板上生长第一外延层。 该层相对轻掺杂，电阻率大于200欧姆·厘米。 然后在第一外延层上生长第二外延层。 第二外延层具有与衬底相反的极性，并且被重掺杂到小于0.005欧姆厘米的电阻率。

    Low cost method of fabricating shallow junction, Schottky semiconductor devices
    6.
    发明授权
    Low cost method of fabricating shallow junction, Schottky semiconductor devices 失效
    低成本的方法制造浅结，肖特基半导体器件

    公开(公告)号：US5635414A

    公开(公告)日：1997-06-03

    申请号：US409762

    申请日：1995-03-28

    申请人： Gregory Zakaluk ,  Dennis Garbis ,  Willem Einthoven ,  Joseph Chan ,  Jack Eng ,  Jun Wu ,  John Amato

    发明人： Gregory Zakaluk ,  Dennis Garbis ,  Willem Einthoven ,  Joseph Chan ,  Jack Eng ,  Jun Wu ,  John Amato

    IPC分类号： H01L21/20 ,  H01L21/285 ,  H01L21/322 ,  H01L21/265

    CPC分类号： H01L21/28537 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3221 ,  Y10S438/974

    摘要： Significant reduction in the cost of fabrication of shallow junction, Schottky or similar semiconductor devices without sacrifice of functional characteristics, while at the same time achieving the advantages is achieved, after the non-polishing cleaning step is essentially performed, by subjecting the substrate to conditions which move disadvantageous factors within said substrate into a space substantially at said surface, followed by substantially removing said factor-containing space from said substrate chemical removal step, followed etching and vapor deposition steps. Although these new steps add time, and therefore cost, to the overall process, the devices under discussion when produced by known industry processes require yet more time, and involve yet more expense, so that the total process represents a substantial reduction in the cost of their manufacture while producing devices which are the equivalent or superior in electrical performance to such devices which are made by known industry processes.

    摘要翻译： 在不牺牲功能特性的情况下显着降低了制造浅结，肖特基或类似半导体器件的成本，同时实现了在基本上执行非抛光清洁步骤之后，通过使基板经受条件 其将所述衬底内的不利因素移动到基本上位于所述表面的空间中，然后在蚀刻和气相沉积步骤之后基本上从所述衬底化学品去除步骤中除去所述含因子空间。 虽然这些新的步骤为整个过程增加了时间，因此增加了成本，但由已知行业流程生产的正在讨论的设备需要更多的时间，并且涉及更多的费用，因此整个过程将大大降低成本 它们的制造同时生产与通过已知工业方法制造的这种装置相当或优越的电气性能的装置。

    Low cost method of fabricating transient voltage suppressor semiconductor devices or the like
    7.
    发明授权
    Low cost method of fabricating transient voltage suppressor semiconductor devices or the like 失效
    制造瞬态电压抑制半导体器件等的低成本方法

    公开(公告)号：US06248651B1

    公开(公告)日：2001-06-19

    申请号：US09103731

    申请日：1998-06-24

    申请人： Jack Eng ,  Joseph Chan ,  Gregory Zakaluk ,  John Amato ,  Dennis Garbis

    发明人： Jack Eng ,  Joseph Chan ,  Gregory Zakaluk ,  John Amato ,  Dennis Garbis

    IPC分类号： H01L21225

    CPC分类号： H01L21/304 ,  H01L21/2252

    摘要： Transient voltage suppressor semiconductor devices and other semiconductor devices having rigorous requirements for the diffusion and depth of impurities to produce P-N junctions can be fabricated at surprisingly low costs without sacrifice of functional characteristics by subjecting the substrate to a grinding process resulting in a surface short of polishing perfection, thereby to eliminate the time-consuming and hence costly conventional polishing operation, and then diffusing the desired impurity into the substrate from a solid impurity source.

    摘要翻译： 对于产生PN结的杂质的扩散和深度的严格要求的瞬态电压抑制器半导体器件和其他半导体器件可以以惊人的低成本制造，而不牺牲功能特性，通过使衬底经受磨削过程，导致表面缺少抛光 从而消除耗时且因此昂贵的常规抛光操作，然后从固体杂质源将所需的杂质扩散到衬底中。

    Gas flow system for CVD reactor
    9.
    发明授权
    Gas flow system for CVD reactor 失效
    CVD反应器气流系统

    公开(公告)号：US5571329A

    公开(公告)日：1996-11-05

    申请号：US411408

    申请日：1995-03-28

    申请人： Joseph Chan ,  Dennis Garbis ,  John Sapio ,  John Latza

    发明人： Joseph Chan ,  Dennis Garbis ,  John Sapio ,  John Latza

    IPC分类号： C23C16/44 ,  C23C16/455 ,  C23C16/00

    CPC分类号： C23C16/45561 ,  C23C16/4401 ,  C23C16/455

    摘要： To minimize contamination of gas flow lines and reactor surfaces from high impurity concentrations present in the CVD reactor, control of the dopant gas supply is located closely adjacent to the reactor input port and the dopant gas supply line is separately vented. First and second dopant gas supplies and a diluent gas supply are connected to branch lines which converge to form the dopant supply line. A solenoid valve is situated in the main dopant supply line as close to the input port as possible. A vent line is connected to the dopant supply line, prior to the solenoid valve. The etchant and silicon gas supplies are each connected to the reactor input by a separate supply line. The etchant and silicon gas supply lines are vented separately from the dopant gas supply line.

    摘要翻译： 为了最小化CVD反应器中存在的高杂质浓度的气体流动管线和反应器表面的污染，掺杂剂气体供应的控制位于反应堆输入端口附近，并且掺杂剂气体供应管线被单独排出。 第一和第二掺杂剂气体供应和稀释气体供应连接到会聚的分支线以形成掺杂剂供应管线。 电磁阀位于主要掺杂剂供应管线中，尽可能靠近输入端口。 在电磁阀之前，排气管线连接到掺杂剂供应管线。 蚀刻剂和硅气体供应各自通过单独的供应管线连接到反应堆输入。 蚀刻剂和硅气体供应管线与掺杂气体供应管线分开排放。