公开(公告)号：US5882986A

公开(公告)日：1999-03-16

申请号：US50106

申请日：1998-03-30

申请人： Jack Eng ,  Joseph Y. Chan ,  Willem G. Einthoven ,  John E. Amato ,  Sandy Tan ,  Lawrence LaTerza ,  Gregory Zakaluk ,  Dennis Garbis

发明人： Jack Eng ,  Joseph Y. Chan ,  Willem G. Einthoven ,  John E. Amato ,  Sandy Tan ,  Lawrence LaTerza ,  Gregory Zakaluk ,  Dennis Garbis

IPC分类号： H01L29/06 ,  H01L21/301 ,  H01L21/304 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/3043

摘要： Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

摘要翻译： 从已知类型的半导体晶片开始，包括平行于晶片的主表面的内部平面p-n结，其中一个晶片表面被氮化硅掩蔽层覆盖。 然后通过掩模层锯切多个相交槽，以形成具有倾斜壁的多个台面，每个台面包括平面p-n结的一部分，其边缘与台面壁相交并暴露。 沟槽壁和暴露的接合边缘是玻璃封装在包括加热晶片的过程中。 然后在不需要图案化蚀刻剂掩模的选择性蚀刻工艺中去除掩模层，并且在台面顶部的现在暴露的硅表面以及晶片的相对表面是金属镀覆的。 然后将晶片沿着平面通过沟槽切割，以提供各自具有玻璃钝化台面的单个芯片。

公开(公告)号：US5360509A

公开(公告)日：1994-11-01

申请号：US21130

申请日：1993-03-08

申请人： Gregory Zakaluk ,  Dennis Garbis ,  Joseph Y. Chan ,  John Latza ,  Lawrence LaTerza

发明人： Gregory Zakaluk ,  Dennis Garbis ,  Joseph Y. Chan ,  John Latza ,  Lawrence LaTerza

IPC分类号： H01L21/20 ,  H01L21/304 ,  H01L21/306

CPC分类号： H01L21/304 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  Y10S438/959

摘要： Significant reductions in the cost of fabrication of epitaxial semiconductor devices without sacrifice of functional characteristics is achieved by eliminating the conventional but costly polishing procedure, instead subjecting the substrate to grinding, cleaning and etching processes in which the grinding removes material from the surface to a depth of at least 65 microns and the etching further removes material to a depth of about 6-10 microns, the grinding preferably being carried out in two steps, the first being a coarse step and the second being a fine step, with the rotated grinding elements dwelling at their respective last grinding positions for a short period of time. The result is the equivalent of the prior art polishing procedure which took considerably longer to carry out and which therefore was much more costly. Complementing this grinding procedure is an improved and cost effective epitaxial process utilizing a unique two-step hydrochloric gas high temperature etch and a faster growth rate process with shorter cycle steps. In addition, oxygen control and "gettering" capabilities result in a total process improving the economics of formation of epitaxial semiconductor devices.

摘要翻译： 通过消除常规但昂贵的抛光方法，可以显着降低外延半导体器件的制造成本，而不牺牲功能特性，而不是对基板进行研磨，清洗和蚀刻工艺，其中研磨将材料从表面移除到深度 至少65微米，并且蚀刻进一步将材料去除至约6-10微米的深度，研磨优选以两个步骤进行，第一步是粗步骤，第二步是精细步骤，旋转的研磨元件 住在他们各自的最后研磨位置很短的时间。 结果相当于现有技术的抛光程序，其花费相当长的时间来执行，因此成本更高。 补充该研磨程序是利用独特的两步盐酸气体高温蚀刻和具有较短循环步骤的更快生长速率工艺的改进且成本有效的外延工艺。 此外，氧气控制和“吸气”能力导致整个工艺改善外延半导体器件形成的经济性。

公开(公告)号：US5298457A

公开(公告)日：1994-03-29

申请号：US82952

申请日：1993-07-01

申请人： William G. Einthoven ,  Joseph Y. Chan ,  Dennis Garbis

发明人： William G. Einthoven ,  Joseph Y. Chan ,  Dennis Garbis

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/304 ,  H01L21/331 ,  H01L29/161 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L21/205

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/977

摘要： The all epitaxial process starts with a high resistivity silicon substrate. Alternating layers of silicon and silicon-germanium are epitaxially grown on the substrate under conditions which create a region with misfit dislocations. A low resistivity silicon layer is then grown over the region. The material is inverted such that the high resistivity layer can be used to form the base of the device. The thickness of the high resistivity layer is adjusted to equal the width of the base of the semiconductor device to be fabricated.

摘要翻译： 所有外延工艺从高电阻率硅衬底开始。 在产生具有失配位错的区域的条件下，在衬底上外延生长硅和硅 - 锗的交替层。 然后在该区域上生长低电阻率硅层。 材料被反转，使得可以使用高电阻率层来形成器件的基极。 将高电阻率层的厚度调整为等于要制造的半导体器件的基极的宽度。

公开(公告)号：US5342805A

公开(公告)日：1994-08-30

申请号：US082951

申请日：1993-07-01

申请人： Joseph Y. Chan ,  Larry Laterza ,  Dennis Garbis ,  William G. Einthoven

发明人： Joseph Y. Chan ,  Larry Laterza ,  Dennis Garbis ,  William G. Einthoven

IPC分类号： H01L21/205 ,  H01L21/20 ,  H01L21/22 ,  H01L21/329 ,  H01L29/165 ,  H01L29/32

CPC分类号： H01L29/66136 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/221 ,  H01L29/165 ,  H01L29/32

摘要： This invention concerns itself with an improved method of producing sharply defined misfit dislocations; (MD) with a new, inexpensive method of doping these misfit dislocations with Au; with invention that a combination of Au and Pt doping in misfit dislocations is superior to any amount of Au and to some specific placements of the misfit dislocations in the device structure.

摘要翻译： 本发明涉及一种改进的产生急剧定义的失配位错的方法; （MD）与一种新的，廉价的方法掺杂这些错配位错与Au; 发明中，在错配位错中Au和Pt掺杂的组合优于任何量的Au以及器件结构中的失配位错的某些特定位置。

公开(公告)号：US4522149A

公开(公告)日：1985-06-11

申请号：US553962

申请日：1983-11-21

申请人： Dennis Garbis ,  Joseph Y. Chan ,  Amedeo J. Granata ,  Robert C. Heller

发明人： Dennis Garbis ,  Joseph Y. Chan ,  Amedeo J. Granata ,  Robert C. Heller

IPC分类号： C23C16/00 ,  C23C16/44 ,  C23C16/458 ,  H01L21/205 ,  C23C13/08

CPC分类号： C23C16/458

摘要： A reactor for use in a chemical vapor deposition process occurring in a radiant absorption heater system employs a vertical gas flow reaction vessel and a novel substantially solid susceptor configured as a truncated wedge. The susceptor is characterized by a high utilized area, resulting in a high wafer capacity and low power requirement.

摘要翻译： 用于在辐射吸收加热器系统中发生的化学气相沉积工艺的反应器使用垂直气流反应容器和构造为截头楔形物的新颖的基本上固体的基座。 基座的特点是利用率高，导致晶圆容量高，功率要求低。

公开(公告)号：US06707339B1

公开(公告)日：2004-03-16

申请号：US10301992

申请日：2002-11-22

申请人： Kiyoshi Kase ,  Joseph Y. Chan ,  Chunhe Zhao

发明人： Kiyoshi Kase ,  Joseph Y. Chan ,  Chunhe Zhao

IPC分类号： H03F345

CPC分类号： H03F3/3023 ,  H03F3/45183 ,  H03F2203/45454 ,  H03F2203/45584 ,  H03F2203/45658

摘要： An operational amplifier circuit (10) uses a first operational amplifier (16) to selectively provide a boosted drive current in response to an input signal voltage transitioning. The boosted driver current is used by a second operational amplifier (22) having a single high gain stage (76). The output drive current of the operational amplifier circuit (10) is increased to a predetermined maximum value for a predetermined time after an input signal transition in order to source increased current to a capacitive or inductive load only during output signal transitions. Separate current boost circuits (30, 70) in each of the first and second operational amplifiers enable early signal transition detection and ensure continuation of increased current until completion of the signal transition.

摘要翻译： 运算放大器电路（10）使用第一运算放大器（16）来响应于输入信号电压转换来选择性地提供升压的驱动电流。 升压的驱动器电流由具有单个高增益级（76）的第二运算放大器（22）使用。 运算放大器电路（10）的输出驱动电流在输入信号转换之后的预定时间内增加到预定的最大值，以便仅在输出信号转换期间将电流增加到电容或电感性负载。 第一和第二运算放大器中的每一个中的独立电流升压电路（30,70）可以实现早期的信号转换检测，并确保持续增加的电流，直到完成信号转换。

公开(公告)号：US06351020B1

公开(公告)日：2002-02-26

申请号：US09438618

申请日：1999-11-12

申请人： Marc L. Tarabbia ,  Joseph Y. Chan ,  Geoffrey B. Hall

发明人： Marc L. Tarabbia ,  Joseph Y. Chan ,  Geoffrey B. Hall

IPC分类号： H01L2900

CPC分类号： H01L29/94 ,  H01L27/0805

摘要： A cumulative capacitor structure with desirably constant capacitance characteristics is disclosed. In one embodiment, the cumulative capacitor includes a set of four capacitors coupled in parallel between first and second terminals of the cumulative capacitor. In one embodiment, the first capacitor is comprised of a top plate formed of an n-type polysilicon coupled to the first terminal, a bottom plate comprised of a first accumulation/depletion region such as an n-well region coupled to the second terminal, and a first dielectric region between its top and bottom plates. The second capacitor has an n-type polysilicon terminal top plate coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plate. A third capacitor has a p-type polysilicon top plate coupled to the first terminal, an accumulation/depletion region bottom plate coupled to the second terminal, and a third dielectric region between its top and bottom plates. The fourth capacitor has a p-type polysilicon terminal coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plates.

摘要翻译： 公开了具有理想的恒定电容特性的累积电容器结构。 在一个实施例中，累积电容器包括在累积电容器的第一和第二端子之间并联耦合的一组四个电容器。 在一个实施例中，第一电容器包括由耦合到第一端子的n型多晶硅形成的顶板，由与第二端子耦合的诸如n阱区域的第一累积/耗尽区域构成的底板， 以及在其顶板和底板之间的第一电介质区域。 第二电容器具有耦合到第二端子的n型多晶硅端子顶板，耦合到第一端子的积聚/耗尽区域底板，以及在其顶板和底板之间的电介质。 第三电容器具有耦合到第一端子的p型多晶硅顶板，耦合到第二端子的累积/耗尽区底板，以及在其顶板和底板之间的第三电介质区域。 第四电容器具有耦合到第二端子的p型多晶硅端子，耦合到第一端子的积累/耗尽区域底板，以及在其顶板和底板之间的电介质。

公开(公告)号：US6137429A

公开(公告)日：2000-10-24

申请号：US265238

申请日：1999-03-08

申请人： Joseph Y. Chan ,  David Yatim ,  Kiyoshi Kase ,  Paul Astrachan

发明人： Joseph Y. Chan ,  David Yatim ,  Kiyoshi Kase ,  Paul Astrachan

IPC分类号： H03M1/08 ,  H03M3/02 ,  H03M3/00

CPC分类号： H03M3/324 ,  H03M3/37 ,  H03M3/50

摘要： A data converter (10) and a method for attenuating noise in an output signal generated by the data converter (10). The data converter (10) includes a sigma-delta modulator (16), a digital-to-analog converter (17), a clock generator (19) connected to the digital-to-analog converter (17), and a clock control circuit (18) connected to the clock generator (19). The clock control circuit (18) enables or disables the clock generator (19) in accordance with the single-bit digital signal to cause a notch characteristic in the output signal for attenuating noise in the output signal.

摘要翻译： 数据转换器（10）和用于衰减由数据转换器（10）产生的输出信号中的噪声的方法。 数据转换器（10）包括Σ-Δ调制器（16），数模转换器（17），连接到数模转换器（17）的时钟发生器（19）和时钟控制 电路（18）连接到时钟发生器（19）。 时钟控制电路（18）根据单比特数字信号启用或禁用时钟发生器（19），以使得输出信号中的陷波特性衰减输出信号中的噪声。

公开(公告)号：US5546047A

公开(公告)日：1996-08-13

申请号：US395126

申请日：1995-02-27

申请人： Joseph Y. Chan ,  Mathew A. Rybicki

发明人： Joseph Y. Chan ,  Mathew A. Rybicki

IPC分类号： H03F3/45 ,  H03F1/32 ,  H03F3/30

CPC分类号： H03F3/3001 ,  H03F2203/30057

摘要： An operational amplifier (10) having an inverted output (20) ranging from a return voltage up to a rail supply voltage includes an amplifying stage (12) and: a linear output inverter (14). The linear output inverter (14) includes an inverting pull down stage (16), an output stage controller (17), and a pull up output stage (18). The inverting pull down stage (16) operates to pull the inverted output down to the return voltage when the inverted output is below a first threshold. The pull up output stage (18) operates to pull the inverted output up to the rail voltage when the inverted output (20) is above a second threshold. The first threshold is greater than the second threshold such that both the inverting pull down stage (16) and the pull up output stage (18) operate when the inverted output (20) lies between the first threshold and the second threshold.

摘要翻译： 具有从返回电压到轨道电源电压范围的反相输出（20）的运算放大器（10）包括放大级（12）和线性输出反相器（14）。 线性输出反相器（14）包括反相下拉级（16），输出级控制器（17）和上拉输出级（18）。 当反相输出低于第一阈值时，反相下拉级（16）操作以将反相输出向下拉到返回电压。 当反相输出（20）高于第二阈值时，上拉输出级（18）操作以将反相输出拉至轨电压。 第一阈值大于第二阈值，使得当反相输出（20）位于第一阈值和第二阈值之间时，反相下拉级（16）和上拉输出级（18）都工作。