公开(公告)号：US06600204B2

公开(公告)日：2003-07-29

申请号：US09903107

申请日：2001-07-11

申请人： Willem G. Einthoven ,  Anthony Ginty ,  Aidan Walsh

发明人： Willem G. Einthoven ,  Anthony Ginty ,  Aidan Walsh

IPC分类号： H01L2900

CPC分类号： H01L29/0607 ,  H01L27/0259 ,  H01L29/66121 ,  H01L29/8618 ,  Y10S438/912 ,  Y10S438/965

摘要： A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown. A method of making such a device is also provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions of the device.

公开(公告)号：US4929987A

公开(公告)日：1990-05-29

申请号：US358883

申请日：1989-05-30

申请人： Willem G. Einthoven

发明人： Willem G. Einthoven

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7838 ,  H01L29/7813

摘要： A wafer with a orientation comprises N layer (middle layer) and a lightly doped P layer (top layer). A strongly doped N layer (source layer) is diffused into most of the top layer. An oxide layer is grown. A V groove with a flat bottom is anisotropically etched through openings in the oxide layer. The V groove is etched through the source layer and most of the P layer. The bottom of the groove initially is at a level above the junction between the top layer and the middle layer. Exposure to beam of phosphorus ions forms a shallow implanted channel region proximate the walls of the groove. An unwanted implanted region along the bottom of the groove is also formed. A second anisotropic etch, through the same oxide mask, deepens the groove bottom to a point below the junction, removing the unwanted portion of the implanted region along the groove bottom. The implanted concentration of the channel is later reduced as the gate oxide is formed. This method of groove formation can be used to set the threshold voltage of enhancement mode power MOSFETS, without compromising the breakdown voltage. It can also be used to produce depletion mode power MOSFETS with zero-gate on resistance values of a few MILLI-OHM CM.sup.2.

摘要翻译： 具有<100>取向的晶片包括N层（中间层）和轻掺杂P层（顶层）。 强掺杂N层（源层）扩散到顶层的大部分。 生长氧化物层。 通过氧化物层中的开口各向异性蚀刻具有平坦底部的V沟槽。 通过源层和大部分P层蚀刻V沟槽。 槽的底部最初处于顶层和中间层之间的连接点的上方。 暴露于磷离子束在凹槽的壁附近形成浅的注入通道区域。 还形成沿凹槽底部的不需要的注入区域。 通过相同的氧化物掩模的第二各向异性蚀刻将凹槽底部加深到接合点下方的一个点，沿凹槽底部移除注入区域的不需要的部分。 随着形成栅极氧化物，沟道的注入浓度随后降低。 沟槽形成的这种方法可用于设置增强型功率MOSFET的阈值电压，而不损害击穿电压。 它也可用于产生具有零MILLI-OHM CM2的零栅导通电阻值的耗尽型功率MOSFET。

公开(公告)号：US4891685A

公开(公告)日：1990-01-02

申请号：US142737

申请日：1988-01-11

申请人： Willem G. Einthoven ,  Muni M. Mitchell

发明人： Willem G. Einthoven ,  Muni M. Mitchell

IPC分类号： H01L29/00 ,  H01L21/329 ,  H01L29/06 ,  H01L29/36 ,  H01L29/861

CPC分类号： H01L29/66136 ,  H01L29/0661 ,  H01L29/36 ,  H01L29/8613 ,  Y10S438/965 ,  Y10S438/978

摘要： A rectifier is fabricated from a P-N junction having a P-type semiconductor layer and an adjacent N-type semiconductor layer. A mesa structure is formed in at least one of said layers. Impurities are deposited at the top of the mesa to form a high concentration region in the surface thereof. The impurities are diffused from the top surface of the mesa toward the P-N junction, whereby the mesa geometry causes the diffusion to take on a generally concave shape as it penetrates into the mesa. The distance between the perimeter of the high concentration region and the wafer substrate is therefore greater than the distance between the central portion of said region and the wafer substrate, providing improved breakdown voltage characteristics and a lower surface field. Breakdown voltage can be measured during device fabrication and precisely controlled by additional diffusions to drive the high concentration region to the required depth.

摘要翻译： 整流器由具有P型半导体层和相邻的N型半导体层的P-N结构成。 在至少一个所述层中形成台面结构。 杂质沉积在台面的顶部以在其表面形成高浓度区域。 杂质从台面的顶表面向P-N结扩散，由此台面几何形状使扩散在其渗入台面时呈现大致凹形的形状。 因此，高浓度区域的周边与晶片衬底之间的距离大于所述区域的中心部分与晶片衬底之间的距离，提供改进的击穿电压特性和较低的表面场。 可以在器件制造期间测量击穿电压，并通过额外的扩散精确控制，以将高浓度区域驱动到所需的深度。

公开(公告)号：US06489660B1

公开(公告)日：2002-12-03

申请号：US09862664

申请日：2001-05-22

申请人： Willem G. Einthoven ,  Lawrence LaTerza ,  Gary Horsman ,  Jack Eng ,  Danny Garbis

发明人： Willem G. Einthoven ,  Lawrence LaTerza ,  Gary Horsman ,  Jack Eng ,  Danny Garbis

IPC分类号： H01L2900

CPC分类号： H01L29/66121 ,  H01L29/8618

摘要： A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p-n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

摘要翻译： 具有对称电流 - 电压特性的双向瞬时电压抑制装置具有第一导电类型的下半导体层，第一导电类型的上半导体层和与下层和上层之间相邻并且设置在下层和上层之间的中间半导体层， 第二相反导电类型，使得形成上部和下部pn结。 中间层具有在接合点之间的中点处最高的净掺杂浓度。 此外，沿着垂直于下层，中层和上层的线的掺杂分布使得在中间层内，中间层的中心平面的一侧上的掺杂分布反映了相对侧上的掺杂分布。 此外，中间层的净掺杂浓度在接合点之间的距离的积分是这样的，当发生故障时，击穿是冲击破坏，而不是雪崩击穿。

公开(公告)号：US4638551A

公开(公告)日：1987-01-27

申请号：US703703

申请日：1985-02-21

申请人： Willem G. Einthoven

发明人： Willem G. Einthoven

IPC分类号： H01L29/06 ,  H01L29/872 ,  H01L29/48

CPC分类号： H01L29/872 ,  H01L29/0619 ,  Y10S148/042 ,  Y10S148/139 ,  Y10S148/14 ,  Y10S438/965

摘要： An improved Schottky barrier device and method of manufacture is disclosed. The device has a semiconductor layer of first conductivity type; an insulating layer covering one face of the semiconductor layer, and has an opening therein. A conductor layer covers the semiconductor layer where the semiconductor layer is exposed by the opening and there forms a recitifying junction with the semiconductor layer. A first region of opposite conductivity type is at the one face of semiconductor layer and extends from where the conductor layer meets the insulating layer and below the conductor layer. A second region of opposite conductivity type is at the one face of semiconductor layer and begins where the conductor layer meets the insulating layer and extending below the insulating layer.

摘要翻译： 公开了一种改进的肖特基势垒器件及其制造方法。 该器件具有第一导电类型的半导体层; 覆盖半导体层的一个面的绝缘层，并且在其中具有开口。 导体层覆盖半导体层，其中半导体层被开口暴露，并且与半导体层形成再结合结。 相反导电型的第一区域位于半导体层的一个面上，并从导体层与绝缘层相遇并在导体层下方延伸。 相反导电类型的第二区域位于半导体层的一个表面，并且开始于导体层与绝缘层相交并延伸到绝缘层下方。

公开(公告)号：US4859621A

公开(公告)日：1989-08-22

申请号：US150755

申请日：1988-02-01

申请人： Willem G. Einthoven

发明人： Willem G. Einthoven

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/7838 ,  Y10S148/051 ,  Y10S148/126 ,  Y10S148/168

摘要： A wafer with a orientation comprises a strongly doped N layer (substrate), a lightly doped N layer (middle layer) and a lightly doped P layer (top layer). A strongly doped N layer (source layer) is diffused into most of the top layer. An oxide layer is grown. A V groove with a flat bottom is anisotropically etched through openings in the oxide layer. The V groove is etched through the source layer and most of the P layer. The bottom of the groove initially is at a level above the junction between the top layer and the middle layer. Exposure to beam of phosphorous ions forms a shallow implanted channel region proximate the walls of the groove. An unwanted implanted region along the bottom of the groove is also formed. A second anisotropic etch, through the same oxide mask, deepens the groove bottom to a point below the junction, removing the unwanted portion of the implanted region along the groove bottom. The implanted concentration of the channel is later reduced as the gate oxide is formed. This method of groove formation can be used to set the threshold voltage of enhancement mode power MOSFETS, without comprising the breakdown voltage. It can also be used to produce depletion mode power MOSFETS with zero-gate on resistance values of a few MILLI-OHM CM.sup.2.

摘要翻译： 具有<100>取向的晶片包括强掺杂N层（衬底），轻掺杂N层（中间层）和轻掺杂P层（顶层）。 强掺杂N层（源层）扩散到顶层的大部分。 生长氧化物层。 通过氧化物层中的开口各向异性蚀刻具有平坦底部的V沟槽。 通过源层和大部分P层蚀刻V沟槽。 槽的底部最初处于顶层和中间层之间的连接点的上方。 暴露于磷离子束形成靠近凹槽壁的浅的注入通道区域。 还形成沿凹槽底部的不需要的注入区域。 通过相同的氧化物掩模的第二各向异性蚀刻将凹槽底部加深到接合点下方的一个点，沿凹槽底部移除注入区域的不需要的部分。 随着形成栅极氧化物，沟道的注入浓度随后降低。 这种沟槽形成方法可用于设置增强型功率MOSFET的阈值电压，不包括击穿电压。 它也可用于产生具有零MILLI-OHM CM2的零栅导通电阻值的耗尽型功率MOSFET。

公开(公告)号：US4742377A

公开(公告)日：1988-05-03

申请号：US922532

申请日：1986-10-23

申请人： Willem G. Einthoven

发明人： Willem G. Einthoven

IPC分类号： H01L29/06 ,  H01L29/872 ,  H01L29/48

CPC分类号： H01L29/872 ,  H01L29/0619

摘要： An improved Schottky barrier device and the method of its manufacture are disclosed. The device comprises a semiconductor layer of first conductivity type, an insulating layer covering one face of the semiconductor layer and having an opening therein, a conductor layer covering the semiconductor layer where it is exposed by the opening and forming a Schottky contact with the semiconductor layer, a first region of opposite conductivity type within the semiconductor layer generally beginning where the conductor layer meets the insulating layer and extending below the conductor layer, and a second region of opposite conductivity type within the semiconductor layer generally beginning where the conductor layer meets the insulting layer and extending below the insulating layer, the second region having a lower concentration of dopants, so that there is formed an asymmetric guard ring, and the opening in the insulating layer has an edge which is bevelled with a slope of between 0.1 and 0.4.

摘要翻译： 公开了一种改进的肖特基势垒器件及其制造方法。 该器件包括第一导电类型的半导体层，覆盖半导体层的一个表面并在其中具有开口的绝缘层，覆盖半导体层的导体层，在该半导体层中暴露于该开口并与半导体层形成肖特基接触 在导体层与绝缘层相遇并延伸到导体层之下的半导体层内的相反导电类型的第一区域，以及半导体层内的相反导电类型的第二区域，通常开始于导体层满足侮辱性 并且在绝缘层下方延伸，第二区域具有较低的掺杂剂浓度，使得形成不对称保护环，并且绝缘层中的开口具有斜率为0.1至0.4的斜面。

公开(公告)号：US4740477A

公开(公告)日：1988-04-26

申请号：US784451

申请日：1985-10-04

申请人： Willem G. Einthoven ,  Muni M. Mitchell

发明人： Willem G. Einthoven ,  Muni M. Mitchell

IPC分类号： H01L29/00 ,  H01L21/329 ,  H01L29/06 ,  H01L29/36 ,  H01L29/861 ,  H01L21/24

CPC分类号： H01L29/66136 ,  H01L29/0661 ,  H01L29/36 ,  H01L29/8613 ,  Y10S438/965 ,  Y10S438/978

摘要： A rectifier is fabricated from a P-N junction having a P-type semiconductor layer and an adjacent N-type semiconductor layer. A mesa structure is formed in at least one of said layers. Impurities are deposited at the top of the mesa to form a high concentration region in the surface thereof. The impurities are diffused from the top surface of the mesa toward the P-N junction, whereby the mesa geometry causes the diffusion to take on a generally concave shape as it penetrates into the mesa. The distance between the perimeter of the high concentration region and the wafer substrate is therefore greater than the distance between the central portion of said region and the wafer substrate, providing improved breakdown voltage characteristics and a lower surface field. Breakdown voltage can be measured during device fabrication and precisely controlled by additional diffusions to drive the high concentration region to the required depth.

摘要翻译： 整流器由具有P型半导体层和相邻的N型半导体层的P-N结构成。 在至少一个所述层中形成台面结构。 杂质沉积在台面的顶部以在其表面形成高浓度区域。 杂质从台面的顶表面向P-N结扩散，由此台面几何形状使扩散在其渗入台面时呈现大致凹形的形状。 因此，高浓度区域的周边与晶片衬底之间的距离大于所述区域的中心部分与晶片衬底之间的距离，提供改进的击穿电压特性和较低的表面场。 可以在器件制造期间测量击穿电压，并通过额外的扩散精确控制，以将高浓度区域驱动到所需的深度。

公开(公告)号：US5882986A

公开(公告)日：1999-03-16

申请号：US50106

申请日：1998-03-30

申请人： Jack Eng ,  Joseph Y. Chan ,  Willem G. Einthoven ,  John E. Amato ,  Sandy Tan ,  Lawrence LaTerza ,  Gregory Zakaluk ,  Dennis Garbis

发明人： Jack Eng ,  Joseph Y. Chan ,  Willem G. Einthoven ,  John E. Amato ,  Sandy Tan ,  Lawrence LaTerza ,  Gregory Zakaluk ,  Dennis Garbis

IPC分类号： H01L29/06 ,  H01L21/301 ,  H01L21/304 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/3043

摘要： Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

摘要翻译： 从已知类型的半导体晶片开始，包括平行于晶片的主表面的内部平面p-n结，其中一个晶片表面被氮化硅掩蔽层覆盖。 然后通过掩模层锯切多个相交槽，以形成具有倾斜壁的多个台面，每个台面包括平面p-n结的一部分，其边缘与台面壁相交并暴露。 沟槽壁和暴露的接合边缘是玻璃封装在包括加热晶片的过程中。 然后在不需要图案化蚀刻剂掩模的选择性蚀刻工艺中去除掩模层，并且在台面顶部的现在暴露的硅表面以及晶片的相对表面是金属镀覆的。 然后将晶片沿着平面通过沟槽切割，以提供各自具有玻璃钝化台面的单个芯片。

公开(公告)号：US4980315A

公开(公告)日：1990-12-25

申请号：US365519

申请日：1989-06-13

申请人： Willem G. Einthoven ,  Linda J. Down

发明人： Willem G. Einthoven ,  Linda J. Down

IPC分类号： H01L21/22 ,  H01L21/329 ,  H01L29/06 ,  H01L29/861 ,  H01L29/866

CPC分类号： H01L29/6609 ,  H01L21/22 ,  H01L29/0657 ,  H01L29/0688 ,  Y10S438/92 ,  Y10S438/965

摘要： A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentraton. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each having a P-N junction intersecting a sidewall of the mesa structure. Then, a layer of oxide is grown on the sidewalls of the mesas, which oxide layer passivates the device. The oxidizing step curves the P-N junction toward the P layer in the vicinity of the oxide layer. Then, the P-N junction is diffused deeper into the P layer with a diffusion front which tends to curve the P-N junction back toward the N layer in the vicinity of the oxide layer. This diffusion is carried out to such an extent as to compensate for the curvature caused by the oxidizing step and thereby substantially flatten the P-N junction. A plurality of successive oxidation/diffusion steps can be undertaken to further flatten the junction adjacent the mesa sidewall. The resultant P-N junction has a greater breakdown voltage in the vicinity of the oxide layer due to the substantial flatness of the P-N junction. The decreased concentration gradient of the linearly graded junction in the vicinity of the oxide layer caused by the oxidizing step increases the breakdown voltage in the vicinity of the oxide layer above the bulk breakdown voltage.