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公开(公告)号：US20120155273A1
公开(公告)日：2012-06-21
申请号：US12968857
申请日：2010-12-15
IPC分类号： H04L12/26
CPC分类号： G06F15/17312
摘要： A multi-chip module configuration includes two processors, each having two nodes, each node including multiple cores or compute units. Each node is connected to the other nodes by links that are high bandwidth or low bandwidth. Routing of traffic between the nodes is controlled at each node according to a routing table and/or a control register that optimize bandwidth usage and traffic congestion control.
摘要翻译： 多芯片模块配置包括两个处理器，每个处理器具有两个节点，每个节点包括多个核心或计算单元。 每个节点通过高带宽或低带宽的链路连接到其他节点。 根据路由表和/或优化带宽使用和业务拥塞控制的控制寄存器，在每个节点处控制节点之间的业务路由。
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2.发明申请METHOD AND INTEGRATED CIRCUIT FOR ADJUSTING THE WIDTH OF AN INPUT/OUTPUT LINK 审中-公开用于调整输入/输出链路宽度的方法和集成电路公开(公告)号：US20130077701A1
公开(公告)日：2013-03-28
申请号：US13243086
申请日：2011-09-23
申请人： Benjamin Tsien , Kevin M. Lepak , Paul C. Miranda , William A. Hughes , Wade L. Williams , Chenping Yang , Adam L. From
发明人： Benjamin Tsien , Kevin M. Lepak , Paul C. Miranda , William A. Hughes , Wade L. Williams , Chenping Yang , Adam L. From
IPC分类号： H04L27/00
CPC分类号： G06F1/3253 , G06F13/4273 , H04L25/14 , H04W28/18 , Y02D10/151
摘要： A method and apparatus are described for adjusting a bit width of an input/output (I/O) link established between a transmitter and a receiver. The I/O link has a plurality of bit lanes. The transmitter may send to the receiver a command identifying at least one selected bit lane of the I/O link that will be powered off or powered on in response to detecting that a bit width adjustment threshold of the I/O link has been reached.
摘要翻译： 描述了一种用于调整在发射机和接收机之间建立的输入/输出（I / O）链路的比特宽度的方法和装置。 I / O链路具有多个位通道。 响应于检测到已经达到I / O链路的比特宽度调整阈值，发射机可以向接收机发送识别I / O链路的至少一个所选比特通道的命令，该I / O链路将被断电或上电。
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公开(公告)号：US20120140768A1
公开(公告)日：2012-06-07
申请号：US12961884
申请日：2010-12-07
IPC分类号： H04L12/56
CPC分类号： H04L49/101 , G06F13/1657 , H04L49/10 , H04L49/1576
摘要： A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.
摘要翻译： 本文描述了具有主要和次要选择器的交叉开关。 交叉开关包括交叉开关命令调度器，其调度将跨越交叉开关从多个源端口路由到多个目的地端口的命令。 交叉开关命令调度器使用主选择器和辅助选择器在每个时钟周期调度两个命令。 交叉开关还可以包括专用响应总线，通用总线和专用命令总线。 系统请求接口可以包括专用命令和数据分组缓冲器以与主要和辅助选择器一起工作。
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公开(公告)号：US08787368B2
公开(公告)日：2014-07-22
申请号：US12961884
申请日：2010-12-07
CPC分类号： H04L49/101 , G06F13/1657 , H04L49/10 , H04L49/1576
摘要： A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.
摘要翻译： 本文描述了具有主要和次要选择器的交叉开关。 交叉开关包括交叉开关命令调度器，其调度将跨越交叉开关从多个源端口路由到多个目的地端口的命令。 交叉开关命令调度器使用主选择器和辅助选择器在每个时钟周期调度两个命令。 交叉开关还可以包括专用响应总线，通用总线和专用命令总线。 系统请求接口可以包括专用命令和数据分组缓冲器以与主要和辅助选择器一起工作。
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