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公开(公告)号：US20120155273A1
公开(公告)日：2012-06-21
申请号：US12968857
申请日：2010-12-15
IPC分类号： H04L12/26
CPC分类号： G06F15/17312
摘要： A multi-chip module configuration includes two processors, each having two nodes, each node including multiple cores or compute units. Each node is connected to the other nodes by links that are high bandwidth or low bandwidth. Routing of traffic between the nodes is controlled at each node according to a routing table and/or a control register that optimize bandwidth usage and traffic congestion control.
摘要翻译： 多芯片模块配置包括两个处理器，每个处理器具有两个节点，每个节点包括多个核心或计算单元。 每个节点通过高带宽或低带宽的链路连接到其他节点。 根据路由表和/或优化带宽使用和业务拥塞控制的控制寄存器，在每个节点处控制节点之间的业务路由。
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公开(公告)号：US08787368B2
公开(公告)日：2014-07-22
申请号：US12961884
申请日：2010-12-07
CPC分类号： H04L49/101 , G06F13/1657 , H04L49/10 , H04L49/1576
摘要： A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.
摘要翻译： 本文描述了具有主要和次要选择器的交叉开关。 交叉开关包括交叉开关命令调度器，其调度将跨越交叉开关从多个源端口路由到多个目的地端口的命令。 交叉开关命令调度器使用主选择器和辅助选择器在每个时钟周期调度两个命令。 交叉开关还可以包括专用响应总线，通用总线和专用命令总线。 系统请求接口可以包括专用命令和数据分组缓冲器以与主要和辅助选择器一起工作。
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公开(公告)号：US20120140768A1
公开(公告)日：2012-06-07
申请号：US12961884
申请日：2010-12-07
IPC分类号： H04L12/56
CPC分类号： H04L49/101 , G06F13/1657 , H04L49/10 , H04L49/1576
摘要： A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.
摘要翻译： 本文描述了具有主要和次要选择器的交叉开关。 交叉开关包括交叉开关命令调度器，其调度将跨越交叉开关从多个源端口路由到多个目的地端口的命令。 交叉开关命令调度器使用主选择器和辅助选择器在每个时钟周期调度两个命令。 交叉开关还可以包括专用响应总线，通用总线和专用命令总线。 系统请求接口可以包括专用命令和数据分组缓冲器以与主要和辅助选择器一起工作。
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公开(公告)号：US20080148135A1
公开(公告)日：2008-06-19
申请号：US11610219
申请日：2006-12-13
IPC分类号： G06F11/07
CPC分类号： H04L1/0061 , H04L1/0079 , H04L1/1829 , H04L2001/0097
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上发送的分组，所述分组包括命令和相关联的分组数据。 耦合到分组调度器并且被配置为在链路上传送分组，并且接口电路被配置为生成覆盖分组的错误检测数据。 接口电路被配置为在分组的末尾发送覆盖分组的错误检测数据，并且还被配置为在分组内插入至少一个部分错误检测数据。 部分错误检测数据覆盖部分错误检测数据之前的分组的一部分。 接收机被配置为接收数据并基于部分CRC校验转发数据。
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公开(公告)号：USRE44487E1
公开(公告)日：2013-09-10
申请号：US13240272
申请日：2011-09-22
CPC分类号： H04L1/0011 , H04L1/0007 , H04L1/0061 , H04L1/18
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。
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公开(公告)号：US07840873B2
公开(公告)日：2010-11-23
申请号：US11610219
申请日：2006-12-13
IPC分类号： H03M13/00
CPC分类号： H04L1/0061 , H04L1/0079 , H04L1/1829 , H04L2001/0097
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上发送的分组，所述分组包括命令和相关联的分组数据。 耦合到分组调度器并且被配置为在链路上传送分组，并且接口电路被配置为生成覆盖分组的错误检测数据。 接口电路被配置为在分组的末尾发送覆盖分组的错误检测数据，并且还被配置为在分组内插入至少一个部分错误检测数据。 部分错误检测数据覆盖部分错误检测数据之前的分组的一部分。 接收机被配置为接收数据并基于部分CRC校验转发数据。
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公开(公告)号：US07881303B2
公开(公告)日：2011-02-01
申请号：US11610191
申请日：2006-12-13
CPC分类号： H04L1/0011 , H04L1/0007 , H04L1/0061 , H04L1/18
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。
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公开(公告)号：US20080148131A1
公开(公告)日：2008-06-19
申请号：US11610191
申请日：2006-12-13
CPC分类号： H04L1/0011 , H04L1/0007 , H04L1/0061 , H04L1/18
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。
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公开(公告)号：US08954635B2
公开(公告)日：2015-02-10
申请号：US13222559
申请日：2011-08-31
CPC分类号： G06F13/36
摘要： A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a communications link using a plurality of virtual channels. A different subset of the plurality of allocated buffers is allocated to each of the virtual channels. The non-allocated buffers are not allocated to a particular virtual channel. The link interface circuit is operable to receive a first transaction over the communications link and assign the first transaction to one of the allocated buffers or one of the non-allocated buffers.
摘要翻译： 一种设备包括链路接口电路，第一多个分配的缓冲器和第二多个未分配的缓冲器。 链路接口电路可操作以使用多个虚拟信道通过通信链路进行通信。 多个分配的缓冲器的不同子集被分配给每个虚拟通道。 未分配的缓冲区不分配给特定的虚拟通道。 链路接口电路可操作以通过通信链路接收第一事务，并将第一事务分配给所分配的缓冲器之一或未分配的缓冲器之一。
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公开(公告)号：US20130054864A1
公开(公告)日：2013-02-28
申请号：US13222559
申请日：2011-08-31
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a communications link using a plurality of virtual channels. A different subset of the plurality of allocated buffers is allocated to each of the virtual channels. The non-allocated buffers are not allocated to a particular virtual channel. The link interface circuit is operable to receive a first transaction over the communications link and assign the first transaction to one of the allocated buffers or one of the non-allocated buffers.
摘要翻译： 一种设备包括链路接口电路，第一多个分配的缓冲器和第二多个未分配的缓冲器。 链路接口电路可操作以使用多个虚拟信道通过通信链路进行通信。 多个分配的缓冲器的不同子集被分配给每个虚拟通道。 未分配的缓冲区不分配给特定的虚拟通道。 链路接口电路可操作以通过通信链路接收第一事务，并将第一事务分配给所分配的缓冲器之一或未分配的缓冲器之一。
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