公开(公告)号：US06753617B2

公开(公告)日：2004-06-22

申请号：US10153527

申请日：2002-05-20

申请人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

发明人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： H01L23544

CPC分类号： G03F9/7065 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

摘要翻译： 一种用于在半导体器件制造工艺中的对准步骤期间在半导体器件，组件或层压体中的不同材料的相邻层之间的界面处发生折射和反射的方法和结果。 该方法包括在半导体器件，组件或层压体的衬底上形成具有第一折射率的材料的平面表面层。 在平坦表面层上形成校正层，然后在校正层上形成具有第二折射率的第二层。 校正层由在第一折射率和第二折射率之间具有中间折射率的材料组成。 该方法还可以被修改为包括插入在任何上述相邻层之间或之上的一层或多层材料和/或中间折射层。 可以通过在最上层上形成具有必要的中间折射率的附加材料层来进一步改进上述方法和所得结构，以进一步减少在最上层与空气之间的界面处发生的反射。 本发明还涉及通过上述方法形成并结合上述结构的半导体器件，组件或层压体。

公开(公告)号：US06242816B1

公开(公告)日：2001-06-05

申请号：US09088322

申请日：1998-06-01

申请人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

发明人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： H01L23544

CPC分类号： G03F9/7065 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

摘要翻译： 一种用于在半导体器件制造工艺中的对准步骤期间在半导体器件，组件或层压体中的不同材料的相邻层之间的界面处发生折射和反射的方法和结果。 该方法包括在半导体器件，组件或层压体的衬底上形成具有第一折射率的材料的平面表面层。 在平坦表面层上形成校正层，然后在校正层上形成具有第二折射率的第二层。 校正层由在第一折射率和第二折射率之间具有中间折射率的材料组成。 该方法还可以被修改为包括插入在任何上述相邻层之间或之上的一层或多层材料和/或中间折射层。 可以通过在最上层上形成具有必要的中间折射率的附加材料层来进一步改进上述方法和所得结构，以进一步减少在最上层与空气之间的界面处发生的反射。 本发明还涉及通过上述方法形成并结合上述结构的半导体器件，组件或层压体。

公开(公告)号：US06501188B1

公开(公告)日：2002-12-31

申请号：US08887547

申请日：1997-07-03

申请人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

发明人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： H01L23544

CPC分类号： G03F9/7065 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

公开(公告)号：US6144109A

公开(公告)日：2000-11-07

申请号：US502925

申请日：2000-02-11

申请人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

发明人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： G03F9/00 ,  H01L23/544

CPC分类号： G03F9/7065 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

公开(公告)号：US6107189A

公开(公告)日：2000-08-22

申请号：US811488

申请日：1997-03-05

申请人： Phillip G. Wald ,  Kunal R. Parekh

发明人： Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76807 ,  H01L2221/1063

摘要： A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface and a conductive runner extends over the active area such that a lower surface of the conductive runner is above and separated from the active area. A widened portion is formed in the conductive runner with an opening formed in the widened portion and self-aligned to edges of the widened portion. A conductive pillar is self-aligned to the opening and extends downward through the opening, through the insulating material, to the active area. The conductive runner provides local interconnection that can be routed over device features formed in and on the structure without using an additional metal layer.

摘要翻译： 一种半导体器件，包括具有形成在该结构的上表面的上表面和接触表面的结构。 在接触表面上形成绝缘材料，并且导电流道在有源区域上延伸，使得导电流道的下表面在有效区域之上并与活性区域分离。 在导电流道中形成加宽部分，其中开口形成在加宽部分中并与加宽部分的边缘自对准。 导电柱与开口自对准，并通过开口向下穿过绝缘材料延伸至有源区。 导电流道提供局部互连，其可以被布置在结构上和结构上形成的器件特征上，而不使用附加的金属层。

公开(公告)号：US06383887B1

公开(公告)日：2002-05-07

申请号：US09724752

申请日：2000-11-28

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively lo forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）基本上选择性地从暴露的未掺杂硅而不是暴露的掺杂硅形成凹凸多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06180485B2

公开(公告)日：2001-01-30

申请号：US09323596

申请日：1999-06-01

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06825095B2

公开(公告)日：2004-11-30

申请号：US09955632

申请日：2001-09-18

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06710390B2

公开(公告)日：2004-03-23

申请号：US09261920

申请日：1999-03-03

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L27108

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06309941B1

公开(公告)日：2001-10-30

申请号：US09765510

申请日：2001-01-19

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的耐磨多晶硅和掺杂的非坚固多晶硅。